JP3312658B2 - Clock phase error detection method and circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock for extracting a timing required for demodulating data from a modulated signal in a multilevel QAM (quadrature amplitude modulation) demodulation used in the field of broadcasting and communication. The present invention relates to a clock phase error detection method and circuit used in a reproduction circuit.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a multi-level QAM demodulator. The synchronous detection circuit 32 performs synchronous orthogonal detection on the QAM signal and outputs an I signal. The synchronous detection circuit 34 performs synchronous orthogonal detection on the QAM signal and outputs a Q signal. Multi-value judgment circuit 3
6 receives the I signal, performs a multi-value determination, and outputs the determination result in the form of parallel data. The multi-level determination circuit 38 receives the Q signal, performs a multi-level determination, and outputs the determination result in the form of parallel data. The parallel-to-serial conversion circuit 40 converts the parallel data output from the multi-value determination circuits 36 and 38 into serial data, and outputs the serial data.

On the other hand, a carrier recovery circuit 42 receives the I signal and the Q signal output from the synchronous detection circuits 32 and 34, and reproduces a reference carrier necessary for the synchronous detection circuits 32 and 34 to perform synchronous quadrature detection. The reproduced reference carrier is supplied directly to the synchronous detection circuit 32 and to the synchronous detection circuit 34 via a π / 2 phase shifter 44. Further, the clock recovery circuit 46 receives either the I signal or the Q signal (I signal in the example of FIG. 4) output from the synchronous detection circuits 32 and 34, and outputs a recovered clock signal.

FIG. 5 shows an example of a conventional clock recovery circuit. The clock phase error detection circuit 50 includes a differentiator 52 for differentiating the I signal (or the Q signal), a square circuit 54 for squaring the output signal of the differentiator 52, that is, full-wave rectification,
A phase comparator 56 compares the phase of the output signal of the squarer 54 and outputs a clock phase error signal. Loop filter 62 converts the clock phase error signal to DC. The voltage controlled oscillator 64 generates a reproduced clock signal having a frequency corresponding to the DC-converted phase error signal.

[0005]

The conventional clock phase error detection circuit shown in FIG. 5 requires a complicated operation such as differentiation and squaring of a pulse train constituting an I or Q signal, so that the circuit configuration is complicated. Problem.

The present invention has been made in view of such a situation, and an object of the present invention is to provide a clock phase error detection method and circuit which can simplify a circuit configuration.

[0007]

A clock phase error detection method according to claim 1 is a clock phase error detection method in multi-level QAM demodulation, wherein one of an I signal and a Q signal obtained by synchronous detection is provided. Is generated by delaying the input signal by one clock time (for example, the signal b of the embodiment), and the second delay signal (for example, the signal of the embodiment) by delaying the first delay signal by one clock time. c) to generate an average signal (for example, signal d in the embodiment) obtained by adding and averaging the input signal and the second delay signal, and subtracting the average signal from the first delay signal to obtain a first difference signal ( For example,
The signal e) of the embodiment is generated, and the input signal is subtracted from the second delay signal to generate a second difference signal (for example, the signal f of the embodiment). When the sign of the second difference signal is positive, the first difference signal is generated. The difference signal is output as a clock phase error signal as it is, and when the sign of the second difference signal is negative, the first difference signal is inverted and output as a clock phase error signal.

A clock phase error detecting circuit according to a second aspect of the present invention is a clock phase error detecting circuit in multi-level QAM demodulation, wherein an input signal which is one of an I signal and a Q signal obtained by synchronous detection is set to one. Delay means (for example, the delay circuits 2 and 6 in the embodiment of FIG. 1) for generating a first delay signal delayed by a clock time and generating a second delay time delayed by one clock time from the first delay signal; Averaging means for generating an averaging signal obtained by averaging the input signal and the second delay signal (for example, the averaging circuit 1 in the embodiment of FIG.
0), subtracting means for subtracting the average signal from the first delayed signal to generate a first difference signal, and subtracting the input signal from the second delayed signal to generate a second difference signal (for example, FIG. 1).
When the sign of the second difference signal is positive, the first difference signal is output as it is as the clock phase error signal when the sign of the second difference signal is positive, and when the sign of the second difference signal is negative, the first difference signal is output. And a selective signal inverting means for inverting the difference signal and outputting it as a clock phase error signal (for example, the inverting circuit 11 in the embodiment of FIG. 1).

A clock phase error detecting circuit according to a third aspect of the present invention is a clock phase error detecting circuit for multi-level QAM demodulation, wherein an input signal which is one of an I signal and a Q signal obtained by synchronous detection is set to one. A first delay element that generates a first delay signal delayed by a clock time (for example, FIG.
D-flip-flop 22), and a second delay element (for example, D-flip-flop 26 in FIG. 2) that generates a second delay signal obtained by delaying the first delay signal by one clock time;
A first arithmetic element (for example, full adder 3 in FIG. 2) that generates an average signal by adding and averaging the input signal and the second delay signal
0), a second arithmetic element (for example, full adder 28 in FIG. 2) for subtracting the average signal from the first delayed signal to generate a first difference signal, and a second arithmetic element for subtracting the input signal from the second delayed signal. When the sign of the third arithmetic element (for example, full adder 24 in FIG. 2) that generates the two difference signal and the second difference signal is positive, the first difference signal is directly output as the clock phase error signal, and the second difference signal is output. When the sign of the difference signal is negative, an exclusive OR gate (for example, the exclusive OR gate 31 in FIG. 2) that inverts the first difference signal and outputs the inverted signal as a clock phase error signal is provided.

[0010]

In the clock phase error detection and circuit method according to the first and second aspects, an input signal which is either an I signal or a Q signal obtained by synchronous detection is delayed by one clock time. One delay signal is generated, the first delay signal is delayed by one clock time, and
A delayed signal is generated, the input signal and the second delayed signal are added and averaged to generate an averaged signal, the averaged signal is subtracted from the first delayed signal to generate a first difference signal, and the second delayed signal is generated. Is subtracted from the input signal to generate a second difference signal. When the sign of the second difference signal is positive, the first difference signal is output as it is as a clock phase error signal, and
When the sign of the difference signal is negative, the first difference signal is inverted and output as a clock phase error signal. As described above, a clock phase error signal can be generated only by simple calculations such as delay, addition, subtraction, and inversion.

In the clock phase error detection circuit according to the third aspect, the first delay element delays the input signal, which is one of the I signal and the Q signal obtained by the synchronous detection, by one clock time. A second delay element generates a delay signal, and the second delay element delays the first delay signal by one clock time to generate a second signal.
A first arithmetic element generates an averaged signal by adding and averaging the input signal and the second delayed signal, and a second arithmetic element generates a delayed average signal by subtracting the averaged signal from the first delayed signal. The third arithmetic element generates a second difference signal by subtracting the input signal from the second delay signal, and the exclusive OR gate generates a second difference signal when the sign of the second difference signal is positive. 1
The difference signal is output as it is as a clock phase error signal,
When the sign of the second difference signal is negative, the first difference signal is inverted and output as a clock phase error signal. Thus, the clock phase error signal can be generated by a simple circuit using the delay element, the operation element such as the full adder, and the exclusive OR gate.

[0012]

FIG. 1 is a block diagram showing the configuration of an embodiment of a clock phase error detection circuit according to the present invention. Delay circuit 2
Is an input signal a which is either the I signal or the Q signal generated by the synchronous detection circuits 32 and 34 of FIG.
A first delay signal b is generated by delaying the clock time, and this signal b is supplied to the input terminal of the delay circuit 6 and
It is supplied to the plus input terminal of the subtraction circuit 8. The speed of the clock signal is twice the data rate of the input signal.

The input signal a is supplied to a minus input terminal of the subtraction circuit 4. The delay circuit 6 delays the first delay signal b by one clock time to generate a second delay signal c, and supplies this signal c to the plus input terminal of the subtraction circuit 4 and to the average value circuit 10. . The average value circuit 10 adds and averages the input signal a and the second delay signal c to generate an averaged signal d, and supplies this signal d to the minus input terminal of the subtraction circuit 8. The subtraction circuit 8 generates a first difference signal e by subtracting the averaging signal d from the first delay signal b, and supplies this signal e to the inversion circuit 11. The subtraction circuit 4 generates a second difference signal f by subtracting the input signal a from the second delay signal c, and supplies a signal indicating the sign of the signal f to the inversion circuit 11.

The inversion circuit 11 outputs the first difference signal e as it is as a clock phase error signal when the sign of the second difference signal f is positive, and outputs the first difference signal when the sign of the second difference signal f is negative. The signal e is inverted and output as a clock phase error signal. When the clock phase error signal has a positive polarity, it indicates that the clock phase is advanced. When the clock phase error signal has a negative polarity, it indicates that the clock phase is delayed. , The degree of clock phase shift.

FIG. 2 shows a 16QAM clock phase error detection circuit by digital signal processing, which is a specific circuit example of the embodiment of FIG. In this example, delay circuits 2 and 6 of FIG.
6, the subtraction circuit 4, the subtraction circuit 8 and the average value circuit 10 of FIG. 1 are respectively composed of full adders 24, 26 and 30, and the inversion circuit 11 of FIG. It is configured.

The full adders 24 and 28 each have 2
Performs subtraction using the complement representation of. The full adder 30 adds the signal a and the signal d and, when supplying the output signal d to the minus input terminal of the full adder 28, shifts the signal d one bit to the right to divide it by two. I have. Exclusive O
The R gate 31 uses the signal indicating the sign of the signal f = ca, that is, the sign bit, and outputs the signal e without inversion when the sign bit is “0”, that is, when the sign bit is positive. If the value is "1", that is, negative, the polarity of the signal e is inverted and output.

FIG. 3 shows an example of an I signal or Q signal which is an input signal and a clock phase error signal which is an output signal of the circuit of FIG. 1 or FIG. The signals input to the circuit in FIG. 2 are digital signals, but in FIG. 3, they are represented in the form of analog signals for easy understanding.
FIG. 3A shows a case where the clock phase is advanced.
, The output signal e of the full adder 28 of FIG.
= B−d is positive, the sign of the output signal f = ca of the subtractor circuit 4 of FIG. 1, that is, the full adder 24 of FIG. 2 is positive, and therefore, the inverting circuit 11 of FIG. The polarity of the clock phase error signal output from the exclusive OR gate 31 is positive, and conversely, when the output signal e = b−d of the subtraction circuit 8 of FIG. 1, that is, the full adder 28 of FIG. The sign of the output signal f = ca of the subtraction circuit 4 of FIG. 1, that is, the full adder 24 of FIG. 2, is negative, and is therefore output from the inversion circuit 11 of FIG. 1, ie, the exclusive OR gate 31 of FIG. The polarity of the clock phase error signal is positive.

FIG. 3B shows a case where there is no clock phase shift, and the output signal e = b−d of the subtraction circuit 8 of FIG. 1, that is, the full adder 28 of FIG. 2 is zero. The value of the clock phase error signal output from the inverting circuit 11, that is, the exclusive OR gate 31 in FIG. 2, is also zero.

FIG. 3 (c) shows a case where the clock phase is delayed. The subtraction circuit 8 shown in FIG. 1, that is, the full adder 28 shown in FIG.
When the output signal e = b−d is positive, the sign of the output signal f = ca of the subtraction circuit 4 of FIG. 1, that is, the full adder 24 of FIG. 2 is negative, and therefore, the inversion circuit 11 of FIG. That is, the polarity of the clock phase error signal output from the exclusive OR gate 31 in FIG. 2 becomes negative, and conversely, the output signal e = b−d of the subtraction circuit 8 in FIG. 1, that is, the full adder 28 in FIG.
Is negative, the sign of the output signal f = ca of the subtractor circuit 4 of FIG. 1, that is, the full adder 24 of FIG. 2, is positive, and therefore, the inverting circuit 11 of FIG. 1, ie, the exclusive OR gate of FIG. The polarity of the clock phase error signal output from 31 is
Becomes negative.

As described above, according to the embodiment of FIG. 1 and the specific example of FIG. 2, it is possible to generate a phase error signal indicating the amount of advance and delay of the clock phase with a simple circuit configuration.

[0021]

According to the clock phase error detection method and circuit of the first and second aspects, the input signal which is either the I signal or the Q signal obtained by the synchronous detection is set to one.
A first delay signal is generated by delaying a clock time, a second delay signal is generated by delaying the first delay signal by one clock time, and an input signal and a second delay signal are added and averaged to obtain an average signal. When the first average signal is subtracted from the first delayed signal to generate a first difference signal, the input signal is subtracted from the second delayed signal to generate a second difference signal, and when the sign of the second difference signal is positive, , The first difference signal is output as it is as the clock phase error signal, and when the sign of the second difference signal is negative, the first difference signal is inverted and output as the clock phase error signal. The clock phase error signal can be generated only by such a simple operation.

According to the clock phase error detection circuit of the third aspect, the input signal which is either the I signal or the Q signal obtained by the synchronous detection is delayed by one clock time, and the first
A first delay element for generating a delay signal;
A second delay element that generates a second delay signal by delaying the clock time, a first arithmetic element that generates an average signal by adding and averaging the input signal and the second delay signal, and an averaging operation from the first delay signal A second subtracting the signal to generate a first difference signal;
An arithmetic element, a third arithmetic element for subtracting the input signal from the second delay signal to generate a second difference signal, and when the sign of the second difference signal is positive, the first difference signal is output as a clock phase error signal as it is. When the sign of the second difference signal is negative, a clock phase error signal is generated by the exclusive OR gate which inverts the first difference signal and outputs the inverted signal as a clock phase error signal. A clock phase error signal can be generated by a simple circuit using an arithmetic element such as the above and an exclusive OR gate.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a clock phase error detection circuit of the present invention.

FIG. 2 is a logic circuit diagram showing a 16QAM clock phase error detection circuit by digital signal processing, which is a specific circuit example of the embodiment of FIG. 1;

FIG. 3 is a diagram illustrating an example of an I signal or a Q signal that is an input signal and a clock phase error signal that is an output signal of the circuit of FIG. 1 or 2;

FIG. 4 is a block diagram illustrating a configuration of a multi-level QAM demodulator.

FIG. 5 is a block diagram illustrating an example of a conventional clock recovery circuit.

[Explanation of symbols]

 Reference Signs List 2 delay circuit 4 subtraction circuit 6 delay circuit 8 subtraction circuit 10 average value circuit 11 inversion circuit 22, 26 D-flip flop 24, 28, 30 full adder 31 exclusive OR gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 27/22 H04L 27/38 H04L 7/00 H04L 7/02

Claims (3)

(57) [Claims] 1. A method for detecting a clock phase error in multi-level QAM demodulation, comprising: generating a first delay signal obtained by delaying an input signal, which is one of an I signal and a Q signal obtained by synchronous detection, by one clock time. Generating a second delay signal obtained by delaying the first delay signal by one clock time, generating an average signal obtained by averaging the input signal and the second delay signal; and generating the average signal from the first delay signal. Subtracting the averaging signal to generate a first difference signal; subtracting the input signal from the second delayed signal to generate a second difference signal; when the sign of the second difference signal is positive, the first difference signal is generated. The clock phase error signal is output as it is, and when the sign of the second difference signal is negative, the first difference signal is inverted and output as a clock phase error signal. Error detection method. 2. A clock phase error detection circuit in multi-level QAM demodulation, wherein a first delay signal is generated by delaying an input signal which is either an I signal or a Q signal obtained by synchronous detection by one clock time. A delay unit that generates a second delay signal obtained by delaying the first delay signal by one clock time; an averaging unit that generates an average signal obtained by averaging the input signal and the second delay signal; Subtraction means for subtracting the averaging signal from the first delay signal to generate a first difference signal, and subtracting the input signal from the second delay signal to generate a second difference signal; When the sign is positive, the first difference signal is output as it is as a clock phase error signal, and when the sign of the second difference signal is negative, the first difference signal is inverted to generate a clock phase error signal. Clock phase error detection circuit, characterized in that it comprises a selective signal inversion means for outputting Te. 3. A clock phase error detection circuit in multi-level QAM demodulation, wherein a first delay signal is generated by delaying an input signal which is either an I signal or a Q signal obtained by synchronous detection by one clock time. A first delay element, a second delay element that generates a second delay signal obtained by delaying the first delay signal by one clock time, and an averaging signal obtained by averaging the input signal and the second delay signal. A first arithmetic element to generate; a second arithmetic element to generate the first difference signal by subtracting the averaging signal from the first delayed signal; and a second difference signal by subtracting the input signal from the second delayed signal. A third arithmetic element that generates the following. When the sign of the second difference signal is positive, the first difference signal is output as it is as a clock phase error signal, and when the sign of the second difference signal is negative, 1 A clock phase error detection circuit comprising: an exclusive OR gate that inverts the difference signal and outputs the inverted signal as a clock phase error signal.