JPH0277150A - クロックライン駆動装置 - Google Patents
クロックライン駆動装置Info
- Publication number
- JPH0277150A JPH0277150A JP22940388A JP22940388A JPH0277150A JP H0277150 A JPH0277150 A JP H0277150A JP 22940388 A JP22940388 A JP 22940388A JP 22940388 A JP22940388 A JP 22940388A JP H0277150 A JPH0277150 A JP H0277150A
- Authority
- JP
- Japan
- Prior art keywords
- clock line
- clock
- driving device
- main
- line driving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22940388A JPH0277150A (ja) | 1988-09-13 | 1988-09-13 | クロックライン駆動装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP22940388A JPH0277150A (ja) | 1988-09-13 | 1988-09-13 | クロックライン駆動装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0277150A true JPH0277150A (ja) | 1990-03-16 |
| JPH0550143B2 JPH0550143B2 (enrdf_load_stackoverflow) | 1993-07-28 |
Family
ID=16891663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP22940388A Granted JPH0277150A (ja) | 1988-09-13 | 1988-09-13 | クロックライン駆動装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0277150A (enrdf_load_stackoverflow) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5532500A (en) * | 1993-09-01 | 1996-07-02 | Nec Corporation | Semiconductor integrated circuit device having clock signal wiring construction for suppressing clock skew |
| US6724679B2 (en) | 2001-10-26 | 2004-04-20 | Renesas Technology Corp. | Semiconductor memory device allowing high density structure or high performance |
| KR100429891B1 (ko) * | 2002-07-29 | 2004-05-03 | 삼성전자주식회사 | 클럭 스큐를 최소화하기 위한 격자형 클럭 분배망 |
| KR100609342B1 (ko) * | 1998-11-10 | 2006-08-09 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 |
-
1988
- 1988-09-13 JP JP22940388A patent/JPH0277150A/ja active Granted
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5532500A (en) * | 1993-09-01 | 1996-07-02 | Nec Corporation | Semiconductor integrated circuit device having clock signal wiring construction for suppressing clock skew |
| KR100609342B1 (ko) * | 1998-11-10 | 2006-08-09 | 가부시키가이샤 히타치세이사쿠쇼 | 반도체 장치 |
| US6724679B2 (en) | 2001-10-26 | 2004-04-20 | Renesas Technology Corp. | Semiconductor memory device allowing high density structure or high performance |
| KR100429891B1 (ko) * | 2002-07-29 | 2004-05-03 | 삼성전자주식회사 | 클럭 스큐를 최소화하기 위한 격자형 클럭 분배망 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0550143B2 (enrdf_load_stackoverflow) | 1993-07-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |