JPH0277150A - Clock line driving device - Google Patents

Abstract

PURPOSE:To enable the decrease in the effective space of logic circuit region of an inner chip to be minimized by a method wherein the length of wirings made to connect the output terminal of an input buffer to respective input terminals of a plurality of main buffers is substantially equalized. CONSTITUTION:Main buffers 2a, 2b, 2c, 2d are arranged in point symmetry with respect to the center of a chip at four corners of the peripheral part of the chip. The output terminal of an input buffer 1 is connected to respective input terminals of the main buffers 2a, 2b, 2c, 2d by wirings 6 in the same length. The respective output terminal of the main buffers 2a, 2b, 2c, 2d are commonly connected to the corner parts P1, P2, P3, P4 of a lattice type clock line 7 evenly covering the inner logic circuit 8 of the chip. If the loads connected to the clock line 7 are evenly distributed on the chip, the respective loads on the main buffers 2a, 2b, 2c, 2d may be equalized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a clock line driving device for driving clock lines wired in a grid pattern in a logic circuit area inside an LSI chip.

(Prior Art) FIG. 4 shows a conventional clock line driving device. The input clock signal is distributed via an input buffer 41 provided in the human output buffer area 47 to a plurality of main buffers 42a, . . . , 41 arranged inside the chip. These main buffers 42a,...42! ! The output signals of are separated from each other by a main clock line 45. However, the load capacitance of each of the main buffers 42a1...42N is adjusted to be equal, and the internal logic cells connected to each of the main buffers 42a,...421 are the same as the main buffers 42a2...42N.
421).

(Problems to be Solved by the Invention) In such a conventional clock line driving device, 1. Since a large number of main buffers 42a, ... 4211 are arranged in the logic circuit area 46 inside the LSI, the internal logic circuit is This reduces the effective area available for gate utility (GATEUTILIT).
V) decreases, and 2, each main buffer 4
2a, ... 41, and that it is technically difficult to arrange these internal logic cells near the main buffer; and 3. from the input buffer 41 to the input terminal of each main buffer. The problem with the shade is that it is difficult to maintain a constant distance between the two.

The present invention has been made in consideration of the above problems, and includes:
To prevent the effective area of the logic circuit area inside the chip from decreasing as much as possible, to equalize the load connected to each main buffer, and to equalize the load connected to each main buffer, and to It is an object of the present invention to provide a clock line driving device that can equalize the distances.

[Structure of the invention]

(Means for Solving the Problems) The present invention provides a clock line driving device for driving clock lines wired in a grid pattern in a logic circuit area inside an LSI chip. A clock buffer consisting of main buffers is provided, and the plurality of main buffers are arranged around the LSI chip in point symmetry with respect to the center of the LSI chip, and the output terminals of each of the plurality of main buffers are wired in a grid pattern. The wires are connected in common at points symmetrical positions with respect to the center of the clock lines, and are provided so that the lengths of the wires connecting the output terminal of the input buffer and the input terminals of each of the plurality of main buffers are substantially equal. It is characterized by being

(Function) According to the clock line driving device according to the present invention configured as described above, the plurality of main buffers are arranged at the periphery of the LSI chip in point symmetry with respect to the center of the LSI chip. The output terminal of each of the plurality of main buffers is connected to a point symmetrical position with respect to the center of the clock line wired in a grid pattern. Furthermore, the lengths of the wiring connecting the output terminal of the input buffer and the input terminals of the plurality of main buffers are substantially equal. As a result, according to the present invention, it is possible not only to prevent a decrease in the effective area of the logic circuit area inside the chip as much as possible, but also to equalize the loads connected to each main buffer, and to The distance to the input terminal of the main buffer can be made equal.

(Embodiment) FIG. 1 shows a first embodiment of a clock line driving device according to the present invention. The clock line driving device of this embodiment includes an input buffer 1 and a plurality of input buffers (four in FIG. 1).
main buffer 2a.

2b, 2c, and 2d. A clock signal is input to input buffer 1. At the periphery 9 of the chip, main buffers 2a, 2b, 2c, and 2d are arranged point-symmetrically with respect to the center of the chip. Main buffers 2a and 2b from the output terminal of the human cover.

The input terminals 2c and 2d are connected to each other by wiring 6 having the same wiring length. Main buffer 2a, 2b, 2
The respective output terminals pl, P2 . Commonly connected to P3 and P4. Assuming that the loads connected to the clock line 7 are uniformly distributed on the chip, the main buffers y2a, 2b, 2c,
The respective loads of 2d are also made uniform. clock line 7
In the above, the clock skew is maximum at the corners of the clock line 7 pl, p2 . p3. p4 and central Po
This is the clock skew between.

As described above, according to the first embodiment, it is possible not only to prevent a decrease in the effective area of the logic circuit area inside the chip as much as possible, but also to equalize the load connected to each main buffer, and to The distance from the output terminal to the input terminal of each main buffer can be made equal.

FIG. 2 shows a second embodiment of the clock line driving device according to the present invention. The difference between this second embodiment and the first embodiment shown in FIG. 1 is that the main buffers 2a, 2b, 2c,
The output terminal of 2d is connected to the inside of the grid-like clock line 7.
Point-symmetrical position P from the center 5. P e , P7
．． It is connected to Pg.

In this case, the clock skew is maximum at the point P5. to which the output terminals of the main buffers 2a, 2b, 2c, and 2d are connected. These are the clock skews between Pa, Py, Pg and the center Po.

As described above, the clock line driving device of the second embodiment can also obtain the same effects as those of the first embodiment.

FIG. 3 shows a third embodiment of the clock line driving device according to the present invention. In this third embodiment, the main buffer 2
A, 2b, 2c, and 2d have a plurality of lead lines from the output terminals, and connect to the grid-like clock line 7 at the connection point P9.
...By increasing the number of PIBs, the maximum value of clock skew within the chip is further reduced. Note that there is a connection point P9 between the lead line from the main buffer and the clock line 7. ...PlB is a point symmetrical position on a concentric circle from the center Po of the chip.

As described above, the clock line driving device of the third embodiment can also obtain the same effects as those of the first embodiment.

〔Effect of the invention〕

According to the present invention, it is possible not only to prevent a decrease in the effective area of the logic circuit area inside the chip as much as possible, but also to equalize the load connected to each main buffer, and also to equalize the load connected to each main buffer from the output terminal of the input buffer. The distances to the input terminals can be made equal.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a first embodiment of a clock line driving device according to the present invention, FIG. 2 is a circuit diagram showing a second embodiment of a clock line driving device according to the present invention, and FIG. 3 is a circuit diagram showing a second embodiment of a clock line driving device according to the present invention. FIG. 4 is a circuit diagram showing a conventional clock line driving device. 1... Input buffer, 2a, 2b, 2C22d...
Main buffer, 6... Wiring, 7... Clock line, 8... Internal logic circuit area, 9... Output buffer area at the chip periphery. Applicant's agent Mr. Sato Figure 1 Figure 2

Claims (1)

[Claims] A clock line driving device that drives clock lines wired in a grid pattern in a logic circuit area inside an LSI chip, which includes a clock buffer consisting of one input buffer and a plurality of main buffers connected in parallel. The plurality of main buffers are arranged on the periphery of the LSI chip in point symmetry with respect to the center of the LSI chip, and the output terminal of each of the plurality of main buffers is connected to the clock wired in the grid pattern. The wires are commonly connected at points symmetrical positions with respect to the center of the line, and are provided so that the lengths of the wires connecting the output terminal of the input buffer and the input terminals of each of the plurality of main buffers are substantially equal. A clock line driving device characterized by: