JPH0536945A - Master slice type semiconductor integrated circuit device - Google Patents
Master slice type semiconductor integrated circuit deviceInfo
- Publication number
- JPH0536945A JPH0536945A JP3192960A JP19296091A JPH0536945A JP H0536945 A JPH0536945 A JP H0536945A JP 3192960 A JP3192960 A JP 3192960A JP 19296091 A JP19296091 A JP 19296091A JP H0536945 A JPH0536945 A JP H0536945A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- basic cell
- output terminal
- area
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はマスタスライス型半導体
集積回路装置に係わり入出力端子と入出力基本セルの配
置構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type semiconductor integrated circuit device and to an arrangement structure of input / output terminals and input / output basic cells.
【０００２】[0002]
【従来の技術】図２に従来の方式に於ける前記入出力端
子と前記入出力基本セルの配置関係図を示す。図中の２
０４は該入出力端子、２０３は該入出力端子２０４の配
置領域であり、２０５は前記入出力基本セルである。前
記入出力端子２０４と前記入出力基本セル２０５は該入
出力基本セル２０５の実現する論理セルが有する固定配
線により接続され、該入出力端子２０４と該入出力基本
セル２０５の間に自由に配線可能な配線領域は存在しな
い。従って、前記入出力端子２０４は前記入出力基本セ
ル２０５の構成要素に等しく該入出力基本セル２０５と
該入出力端子２０４の位置関係が全入出力基本セルに於
いて共通であり任意の配置関係にある入出力基本セル２
０５と入出力端子２０４を接続することは考慮されてい
ない。2. Description of the Related Art FIG. 2 is a layout diagram of the input / output terminals and the input / output basic cells in a conventional system. 2 in the figure
Reference numeral 04 is the input / output terminal, 203 is an arrangement region of the input / output terminal 204, and 205 is the input / output basic cell. The input / output terminal 204 and the input / output basic cell 205 are connected by a fixed wiring included in a logic cell realized by the input / output basic cell 205, and a free wiring is provided between the input / output terminal 204 and the input / output basic cell 205. There is no possible wiring area. Therefore, the input / output terminal 204 is equal to the constituent element of the input / output basic cell 205, and the positional relationship between the input / output basic cell 205 and the input / output terminal 204 is common to all the input / output basic cells, and an arbitrary layout relationship is provided. I / O basic cell 2 at
No connection between 05 and the input / output terminal 204 is considered.
【０００３】[0003]
【発明が解決しようとする課題】上記従来技術では半導
体基板の角隅に位置するコーナー領域は前記入出力基本
セルが配置不可能の領域であり、該入出力基本セルと一
定の位置関係を有する前記入出力端子に関しても配置不
可能となる。また、入出力端子を配置するには半導体基
板の大きさ、前記入出力基本セル位置、前記入出力端子
位置のより複数個の固定配線パターンを用意する必要が
ありセルライブラリが増大するという問題点を有する。In the above-mentioned prior art, the corner regions located at the corners of the semiconductor substrate are regions in which the input / output basic cells cannot be arranged and have a fixed positional relationship with the input / output basic cells. The input / output terminals cannot be arranged. Further, in order to arrange the input / output terminals, it is necessary to prepare a plurality of fixed wiring patterns depending on the size of the semiconductor substrate, the input / output basic cell positions, and the input / output terminal positions, which increases the cell library. Have.
【０００４】そこで本発明はこのような問題点を解決す
るためのもので其の目的とするところはマスタスライス
方式のゲートアレイでセルライブラリを増大する事なく
半導体基板の角隅に位置するコーナー領域に入出力端子
を配置することが可能となる入出力端子、入出力基本セ
ルの配線構造を提供することが目的である。Therefore, the present invention is intended to solve such a problem, and an object of the present invention is to provide a master slice type gate array in a corner region located at a corner of a semiconductor substrate without increasing a cell library. It is an object of the present invention to provide an input / output terminal and an input / output basic cell wiring structure in which the input / output terminal can be arranged.
【０００５】[0005]
【課題を解決するための手段】半導体基板上に論理を構
成する基本セルと入出力論理を構成する入出力基本セル
及びパッケージに直接電気的に接続される入出力端子が
規則的に配置されるマスタスライス方式のゲートアレイ
に於いて、該入出力端子の配置領域が該入出力基本セル
の配置領域の外側に存在し該入出力端子の配置領域と該
入出力基本セルの配置領域の間に配線領域が存在するこ
とを特徴とする。SUMMARY OF THE INVENTION On a semiconductor substrate, a basic cell forming logic, an input / output basic cell forming input / output logic, and an input / output terminal directly electrically connected to a package are regularly arranged. In the master slice type gate array, the arrangement area of the input / output terminals exists outside the arrangement area of the input / output basic cells, and is arranged between the arrangement area of the input / output terminals and the arrangement area of the input / output basic cells. It is characterized in that there is a wiring region.
【０００６】[0006]
【実施例】図１に本発明の入出力端子と入出力基本セル
間の接続配線を設定する配線領域と該入出力端子の配置
領域及び該入出力基本セルの配置領域の配置関係図を示
す。前記入力端子１０４より構成される入力端子配置領
域１０３と前記入出力基本セル１０５の配置領域の間に
本発明の該入出力端子１０４と該入出力基本セル１０５
の接続を目的とする金属配線を設定する配線領域１０６
が配置されている。前記入出力端子１０４と前記入出力
基本セル１０５は金属配線により接続されるため配置位
置は特定の配置関係を有しない。従って前記入出力端子
配置領域１０３内の任意の位置に前記入出力端子１０４
を設定できる。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a layout relation diagram of a wiring area for setting a connection wiring between an input / output terminal and an input / output basic cell of the present invention, an arrangement area of the input / output terminal and an arrangement area of the input / output basic cell. .. The input / output terminal 104 and the input / output basic cell 105 of the present invention are provided between the input terminal arrangement area 103 composed of the input terminal 104 and the arrangement area of the input / output basic cell 105.
Area 106 for setting metal wiring for the purpose of connecting
Are arranged. Since the input / output terminal 104 and the input / output basic cell 105 are connected by a metal wiring, the arrangement position does not have a specific arrangement relation. Therefore, the input / output terminal 104 is placed at an arbitrary position in the input / output terminal placement area 103.
Can be set.
【０００７】図３に本発明の前記コーナー領域に於ける
接続配線図を示す。図３に於ける３０２と３０３は前記
入出力端子、３０７は前記入出力基本セルであり、３０
９は本発明の該入出力端子３０３と該入出力基本セル３
０７接続用金属配線配置領域である。図３に於て外部か
らの信号は前記入出力端子３０２から接続端子３１２、
本発明の金属配線配置領域３０９内に配線された金属配
線３０４、接続端子３１０を介して前記入出力基本セル
３０６に入力され、入力論理回路、接続端子３１４、金
属配線３１６により、前記基本セル領域３０１に入力さ
れる。また、前記基本セル領域３０１より出力される信
号は金属配線３１７、接続端子３１５を介して前記入出
力基本セル３０７に入力され、出力論理回路、接続端子
３１１、前記金属配線配置領域３０９内に配線された金
属配線３０５、接続端子３１３を介して前記入出力端子
３０３により外部に出力される。FIG. 3 shows a connection wiring diagram in the corner region of the present invention. In FIG. 3, 302 and 303 are the input / output terminals, 307 is the input / output basic cell, and 30
9 is the input / output terminal 303 and the input / output basic cell 3 of the present invention.
07 is a metal wiring arrangement region for connection. In FIG. 3, signals from the outside are transferred from the input / output terminal 302 to the connection terminal 312,
The basic cell region is input to the input / output basic cell 306 through the metal wiring 304 and the connection terminal 310 wired in the metal wiring arrangement area 309 of the present invention, and is input by the input logic circuit, the connection terminal 314, and the metal wiring 316. It is input to 301. A signal output from the basic cell region 301 is input to the input / output basic cell 307 via a metal wiring 317 and a connection terminal 315, and is output to the output logic circuit, the connection terminal 311, and the metal wiring arrangement area 309. The data is output to the outside through the input / output terminal 303 via the metal wiring 305 and the connection terminal 313 which are formed.
【０００８】[0008]
【発明の効果】以上記したように本発明によれば、マス
タスライス方式のゲートアレイに於いて該ゲートアレイ
の半導体基板に対して効率よく最大数の入力端子を配置
することができるという効果を有する。また、入出力端
子位置と関係なく入出力基本セルの位置を決定できるた
め、該入出力基本セルが構成する論理、必要な電流量に
応じて其の入出力基本セルをチップ内に配置することが
可能であるという効果を有する。As described above, according to the present invention, in a master slice type gate array, the maximum number of input terminals can be efficiently arranged on the semiconductor substrate of the gate array. Have. Further, since the position of the input / output basic cell can be determined regardless of the position of the input / output terminal, the input / output basic cell should be arranged in the chip according to the logic formed by the input / output basic cell and the required current amount. Has the effect that it is possible.
【図１】本発明の入出力端子と入出力基本セル間の接続
配線を設定する配線領域と該入出力端子の配置領域及び
該入出力基本セルの配置領域の配置関係図である。FIG. 1 is a layout relationship diagram of a wiring area for setting a connection wiring between an input / output terminal and an input / output basic cell of the present invention, an arrangement area of the input / output terminal, and an arrangement area of the input / output basic cell.
【図２】従来の方式に於ける前記入出力端子と前記入出
力基本セルの配置関係図である。FIG. 2 is a layout relationship diagram of the input / output terminals and the input / output basic cells in a conventional system.
【図３】本発明の前記コーナー領域に於ける接続配線図
である。FIG. 3 is a connection wiring diagram in the corner region of the present invention.
【符号の説明】 １０１、２０１ ・・・ 半導体基板 １０２、２０２、３０１ ・・・ 基本セル領域 １０３、２０３、３０８ ・・・ 入出力端子配置領域 １０４、２０４、３０２、３０３ ・・・ 入出力端子 １０５、２０５、３０６、３０７ ・・・ 入出力基本
セル １０６、３０９ ・・・ 入出力端子−入出力基本セル
間配線領域 ３０４、３０５ ・・・ 入出力端子−入出力基本セル
間配線 ３１６、３１７ ・・・ 金属配線 ３１０、３１１、３１２、３１３、３１４、３１５ ・
・・ 配線接続端子[Explanation of reference numerals] 101, 201 ... Semiconductor substrate 102, 202, 301 ... Basic cell area 103, 203, 308 ... Input / output terminal arrangement area 104, 204, 302, 303 ... Input / output terminal 105, 205, 306, 307 ... Input / output basic cell 106, 309 ... Input / output terminal-input / output basic cell wiring area 304, 305 ... Input / output terminal-input / output basic cell wiring 316, 317 ... Metal wiring 310, 311, 312, 313, 314, 315
..Wiring connection terminals
Claims (1)
と入出力論理を構成する入出力基本セル及びパッケージ
に直接電気的に接続される入出力端子が規則的に配置さ
れるマスタスライス方式のゲートアレイに於いて、該入
出力端子の配置領域が該入出力基本セルの配置領域の外
側に存在し該入出力端子の配置領域と該入出力基本セル
の配置領域の間に配線領域が存在することを特徴とする
マスタスライス型半導体集積回路装置。1. A master slice system in which a basic cell forming a logic, an input / output basic cell forming an input / output logic, and an input / output terminal directly electrically connected to a package are regularly arranged on a semiconductor substrate. In the gate array, the arrangement area of the input / output terminals exists outside the arrangement area of the input / output basic cells, and the wiring area exists between the arrangement area of the input / output terminals and the arrangement area of the input / output basic cells. A master slice type semiconductor integrated circuit device characterized by the above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3192960A JPH0536945A (en) | 1991-08-01 | 1991-08-01 | Master slice type semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3192960A JPH0536945A (en) | 1991-08-01 | 1991-08-01 | Master slice type semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0536945A true JPH0536945A (en) | 1993-02-12 |
Family
ID=16299899
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3192960A Pending JPH0536945A (en) | 1991-08-01 | 1991-08-01 | Master slice type semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0536945A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100224671B1 (en) * | 1996-12-13 | 1999-10-15 | 윤종용 | Master slice structure of gate array |
-
1991
- 1991-08-01 JP JP3192960A patent/JPH0536945A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100224671B1 (en) * | 1996-12-13 | 1999-10-15 | 윤종용 | Master slice structure of gate array |
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