JPH0250498B2 - - Google Patents

Info

Publication number
JPH0250498B2
JPH0250498B2 JP56119700A JP11970081A JPH0250498B2 JP H0250498 B2 JPH0250498 B2 JP H0250498B2 JP 56119700 A JP56119700 A JP 56119700A JP 11970081 A JP11970081 A JP 11970081A JP H0250498 B2 JPH0250498 B2 JP H0250498B2
Authority
JP
Japan
Prior art keywords
address
data
cache memory
memory
address counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP56119700A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5819785A (ja
Inventor
Masaaki Kobayashi
Shigeru Hashimoto
Takumi Kishino
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56119700A priority Critical patent/JPS5819785A/ja
Publication of JPS5819785A publication Critical patent/JPS5819785A/ja
Publication of JPH0250498B2 publication Critical patent/JPH0250498B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP56119700A 1981-07-30 1981-07-30 メモリアクセス制御方式 Granted JPS5819785A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56119700A JPS5819785A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56119700A JPS5819785A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Publications (2)

Publication Number Publication Date
JPS5819785A JPS5819785A (ja) 1983-02-04
JPH0250498B2 true JPH0250498B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-11-02

Family

ID=14767905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56119700A Granted JPS5819785A (ja) 1981-07-30 1981-07-30 メモリアクセス制御方式

Country Status (1)

Country Link
JP (1) JPS5819785A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61258063A (ja) * 1985-05-07 1986-11-15 日本染色機械株式会社 長尺繊維製品処理装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5435741B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) * 1973-12-28 1979-11-05
JPS5816263B2 (ja) * 1975-11-28 1983-03-30 株式会社日立製作所 ジヨウホウシヨリソウチ
JPS53134335A (en) * 1977-04-28 1978-11-22 Fujitsu Ltd Memory control system
JPS5680871A (en) * 1979-12-06 1981-07-02 Fujitsu Ltd Buffer memory control system

Also Published As

Publication number Publication date
JPS5819785A (ja) 1983-02-04

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