JPH0247102B2 - - Google Patents
Info
- Publication number
- JPH0247102B2 JPH0247102B2 JP60104035A JP10403585A JPH0247102B2 JP H0247102 B2 JPH0247102 B2 JP H0247102B2 JP 60104035 A JP60104035 A JP 60104035A JP 10403585 A JP10403585 A JP 10403585A JP H0247102 B2 JPH0247102 B2 JP H0247102B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- insulating layer
- multilayer wiring
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02137—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising alkyl silsesquioxane, e.g. MSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
Priority Applications (9)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60104035A JPS61292342A (ja) | 1985-05-17 | 1985-05-17 | 多層配線構造体の製法 |
US06/790,615 US4670299A (en) | 1984-11-01 | 1985-10-23 | Preparation of lower alkyl polysilsesquioxane and formation of insulating layer of silylated polymer on electronic circuit board |
KR1019850007985A KR880000853B1 (ko) | 1984-11-01 | 1985-10-29 | 저급알킬 폴리실세스퀴옥산의 제조방법 |
DE8585307905T DE3587041T2 (de) | 1984-11-01 | 1985-10-31 | Verfahren zur herstellung von isolatorschichten aus silylierten polysilsesquioxanen auf elektronischen gedruckten schaltung. |
DE90114892T DE3587442T2 (de) | 1984-11-01 | 1985-10-31 | Verfahren zur Herstellung von Polysilsesquioxanen. |
EP19900114892 EP0406911B1 (en) | 1984-11-01 | 1985-10-31 | Process for preparation of polysilsesquioxane |
EP19850307905 EP0198976B1 (en) | 1984-11-01 | 1985-10-31 | Process for formation of insulating layer of silylated polysilsesquioxane on electronic circuit board |
KR1019870014659A KR900005894B1 (ko) | 1984-11-01 | 1987-12-21 | 표면이 평평한 절연층의 형성방법 |
US07/281,926 US4988514A (en) | 1984-11-01 | 1988-12-02 | Preparation of lower alkyl polysilsesquioxane and formation of insulating layer of silylated polymer on electronic circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP60104035A JPS61292342A (ja) | 1985-05-17 | 1985-05-17 | 多層配線構造体の製法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61292342A JPS61292342A (ja) | 1986-12-23 |
JPH0247102B2 true JPH0247102B2 (enrdf_load_stackoverflow) | 1990-10-18 |
Family
ID=14369970
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP60104035A Granted JPS61292342A (ja) | 1984-11-01 | 1985-05-17 | 多層配線構造体の製法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61292342A (enrdf_load_stackoverflow) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6440550B1 (en) | 1999-10-18 | 2002-08-27 | Honeywell International Inc. | Deposition of fluorosilsesquioxane films |
US6368400B1 (en) | 2000-07-17 | 2002-04-09 | Honeywell International | Absorbing compounds for spin-on-glass anti-reflective coatings for photolithography |
US8053159B2 (en) | 2003-11-18 | 2011-11-08 | Honeywell International Inc. | Antireflective coatings for via fill and photolithography applications and methods of preparation thereof |
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1985
- 1985-05-17 JP JP60104035A patent/JPS61292342A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS61292342A (ja) | 1986-12-23 |