JPH02280366A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH02280366A
JPH02280366A JP1102841A JP10284189A JPH02280366A JP H02280366 A JPH02280366 A JP H02280366A JP 1102841 A JP1102841 A JP 1102841A JP 10284189 A JP10284189 A JP 10284189A JP H02280366 A JPH02280366 A JP H02280366A
Authority
JP
Japan
Prior art keywords
die pad
upper face
semiconductor device
wire
gold wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1102841A
Other languages
English (en)
Inventor
Norio Koutou
杭東 詔夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP1102841A priority Critical patent/JPH02280366A/ja
Publication of JPH02280366A publication Critical patent/JPH02280366A/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4899Auxiliary members for wire connectors, e.g. flow-barriers, reinforcing structures, spacers, alignment aids
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01047Silver [Ag]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、リードフレームを有するパッケージの半導体
装置に関する。
従来の技術 従来のダイパットを有するリードフレームを利用したプ
ラスチックパッケージ式の半導体装置では、第4図に示
すように、リードフレームのダイパット1に半導体素子
のチップ4を銀ペースト5や金−シリコン共晶法にて接
着し、金線6をリードフレームのインナーリード3に接
続していた。
発明が解決しようとする課題 ところで、上記方法は、最も簡素で一般的であるが、近
年チップサイズが小さくなり、また多ビン化の方向にな
るにつれ、チップ4とリードフレームのインナーリード
3とを結ぶ金線6の長さがダイパット1とインナーリー
ド3との間の間隔に比べて長くなってきた。金線6が長
くなると金線6が垂れてダイパット1に接触してショー
ト不良になることが多くあった。
金線6の垂れを少なくする方法として、金線6のループ
高さを高くする方法があるが5ループを高くすると、樹
脂封止時に樹脂が金線6を押し倒してループ変形が生じ
やすくなり、インナーリード3間のショート不良が発生
する。
本発明は上記問題を解決するもので、ショート不良を生
じることのない半導体装置を提供することを目的とする
ものである。
課題を解決するための手段 上記問題を解決するために本発明は、チップを搭載する
リードフレームのダイパットの上面周辺部に絶縁シート
や絶R塗料からなる絶縁材を設けたものである。
作用 上記構成により、ダイパットの上面周辺部が絶縁材によ
り絶縁されているため、チップからインナーリードにボ
ンディングした金線が垂れてダイパット上の絶縁材に接
触しても、金線とダイパットとは電気的に絶縁された状
態に保たれ、ショート不良は生じなくなる。
実施例 以下、本発明の一実施例を図面に基づき説明する。
第1図は本発明の一実施例を示す半導体装置の断面図、
第2図および第3図は同半導体装置のリードフレームの
平面図および断面図であり、従来のものと同じ部材には
同一番号を付し、第1図〜第3図において、QFP10
0ピン型パッケージの半導体装置の場合について説明す
る。第1図〜第3図に示すように、鉄−ニッケル(42
70イ)製のリードフレームのサイズ8.5 X 8.
5mmのダイパット1における上面周辺部には、ポリイ
ミド製の絶縁テープ2が、内寸7.OX 7.Om、外
寸8.8X8.8mmの額縁状に切断されてアクリル系
接着剤を介して接着されている。ダイパット1の上面中
央部には銀ペースト5がデイスペンサにて塗布され、チ
ップサイズ6.5X6.5nwaのシリコンチップ4が
ダイボンドされている。シリコンチップ4のボンディン
グパットとインナーリード3とは直径35μm、長さ3
.3mmの金線6により接続されている。
上記構成において、金線6はダイパット1の上面周辺箇
所に垂れて接触することがあるが、この箇所には絶縁テ
ープ2が設けられているため、金線6とダイパット1と
のショート不良は生じない。
発明の効果 以上のように、本発明によれば、ダイパット上面の周辺
部を絶縁材によって絶縁することにより、ワイヤーボン
ドの金線が垂れてダイパットに接触しても電気的なショ
ート不良とはならない。これにより、半導体装置の信頼
性が向上する。
【図面の簡単な説明】
第1図は本発明の一実施例を示す半導体Mllの断面図
、第2図および第3図は同半導体装置のリードフレーム
の平面図および断面図、第4図は従来の半導体装置を示
す断面図である。 1・・・ダイパット、2・・・絶縁テープ、3・・・イ
ンナーリード、4・・・シリコンチップ、6・・・金線
。 代理人   森  本  義  弘 インチ一り−V゛ り 第4図

Claims (1)

    【特許請求の範囲】
  1. 1、チップを搭載するリードフレームのダイパットの上
    面周辺部に絶縁材を設けた半導体装置。
JP1102841A 1989-04-20 1989-04-20 半導体装置 Pending JPH02280366A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1102841A JPH02280366A (ja) 1989-04-20 1989-04-20 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1102841A JPH02280366A (ja) 1989-04-20 1989-04-20 半導体装置

Publications (1)

Publication Number Publication Date
JPH02280366A true JPH02280366A (ja) 1990-11-16

Family

ID=14338199

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1102841A Pending JPH02280366A (ja) 1989-04-20 1989-04-20 半導体装置

Country Status (1)

Country Link
JP (1) JPH02280366A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030075788A (ko) * 2002-03-20 2003-09-26 세미웰반도체 주식회사 반도체 패키지 구조

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20030075788A (ko) * 2002-03-20 2003-09-26 세미웰반도체 주식회사 반도체 패키지 구조

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