JPH02222563A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH02222563A
JPH02222563A JP4454789A JP4454789A JPH02222563A JP H02222563 A JPH02222563 A JP H02222563A JP 4454789 A JP4454789 A JP 4454789A JP 4454789 A JP4454789 A JP 4454789A JP H02222563 A JPH02222563 A JP H02222563A
Authority
JP
Japan
Prior art keywords
wiring board
board
ceramic
electrode
external lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4454789A
Other languages
English (en)
Inventor
Hiromi Sakata
坂田　博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP4454789A priority Critical patent/JPH02222563A/ja
Publication of JPH02222563A publication Critical patent/JPH02222563A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Landscapes

  • Casings For Electric Apparatus (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は有機配線基板上に半導体チップを搭載した混成
集積回路に関する。
〔従来の技術〕
従来、この種の混成集積回路は、例えば第３図に示すよ
うに、ガラスエポキシ基板１上に半導体チップ５をＡｇ
ペースト４でグイボンディングした後、Ａｕ線６による
ワイヤポンディングを行ないプリコート樹脂１２等で封
止した構造となっていた。
〔発明が解決しようとする課題〕
上述した従来の混成集積回路は、ガラスエポキシ基板自
身の吸湿性が高いため、高温高温バイアス試験などの耐
湿性試験でセラミック基板を用いた混成集積回路に比べ
がなり劣るという欠点がある。
〔課題を解決するための手段〕
本発明の混成集積回路は、半導体チップを接続した有機
配線基板が外部引出電極を有するセラミック基板上に搭
載され、前記有機配線基板側の電極と前記外部引出電極
とが電気的に接続され、前記有機配線基板の外側をセラ
ミックで覆い封止したことを特徴とする。
〔実施例〕
次に、本発明について図面を参照して説明する。
第１図は本発明の一実施例の断面図である。ガラスエポ
キシ多層配線基板１上に半導体チップ５をＡｇペースト
４でダイポンディングを行う。次に、外部引出し電極７
を形成したセラミック基板２上に前記のガラスエポキシ
多層基板１をシリコン樹脂８で接着し、半導体チップ５
．ガラスエポキシ多層基板の電極３及び外部引出し電極
７の相互間をＡｕ線６で公知のワイヤポンディング法に
より接続する。次に、シール樹脂１０を塗布したセラミ
ックキャップ９を被せて窒素雰囲気中で１５０℃〜１７
０℃の温度で２〜３時間加熱し封止する。更に、外部端
子１１を取付は半田付けを行なう。こうして得られた混
成集積回路は、温度８５℃湿度８５％印加電圧５ｖの高
温高湿バイアス試験で１００ＯＨをクリアする事が可能
となり従来構造に比べ耐湿性が格段に向上した。
第２図は本発明の他の実施例の断面図である。
４層〜６層からなるガラスエポキシ多層配線基板ｌに半
導体チップ５を搭載しＡｕ線６をワイヤポンディングし
プリフート樹脂１２を塗布し加熱硬化する。次に前記基
板と引出し電極７を設けたセラミック基板２をリフロー
法によりはんだ１３で接続する。以降該−実施例と同様
にセラミックキャップ封止を行ない外部端子を取付けて
成る。
この実施例ではガラスエポキシ多層基板に搭載された半
導体チップが樹脂コートされているので組立作業での取
扱いが容易となり作業能率が向上するという利点がある
。又、はんだによる電気的接続と同時に基板との接着も
兼ねる効果も有する。
〔発明の効果〕
以上説明したように本発明は、半導体チップが接続され
たガラスエポキシ多層基板をセラミック基板及びセラミ
ックキャップで封止する事により、特に耐湿性が改善さ
れ高信頼性の混成集積回路が得られる。
【図面の簡単な説明】
第１図及び第２図はそれぞれ本発明の混成集積回路の一
実施例及び他の実施例の断面図、第３図は従来の混成集
積回路の断面図である。 １・・・・・・ガラスエポキシ多層配線基板、２・・・
・・・セラミック基板、３・・・・・・電極、４・・・
・・・Ａｇペースト、５・・・・・・半導体チップ、６
・・・・・・Ａｕ線、７・・・・・・外部引出し電極、
８・・・・・・シリコン樹脂、９・・・・・・セラミッ
クキャップ、１０・・・・・・シール樹脂、１１・・・
・・・外部端子、１２・・・・・・プリコート樹脂、１
３・・・・・・はんだ。 代理人　弁理士　　内　原　　　晋 第１図 第３図

Claims (1)

    【特許請求の範囲】
  1. 　半導体チップを接続した有機配線基板が外部引出し電
    極を有するセラミック基板に搭載され、前記有機配線基
    板側の電極と前記外部引出し電極とが電気的に接続され
    、前記有機配線基板の外側をセラミックキャップで覆い
    封止したことを特徴とする混成集積回路。
JP4454789A 1989-02-23 1989-02-23 混成集積回路 Pending JPH02222563A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4454789A JPH02222563A (ja) 1989-02-23 1989-02-23 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4454789A JPH02222563A (ja) 1989-02-23 1989-02-23 混成集積回路

Publications (1)

Publication Number Publication Date
JPH02222563A true JPH02222563A (ja) 1990-09-05

Family

ID=12694526

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4454789A Pending JPH02222563A (ja) 1989-02-23 1989-02-23 混成集積回路

Country Status (1)

Country Link
JP (1) JPH02222563A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08503423A (ja) * 1992-11-23 1996-04-16 ギューリング，ヨーク 交換可能な切削チップを備えたドリル

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08503423A (ja) * 1992-11-23 1996-04-16 ギューリング，ヨーク 交換可能な切削チップを備えたドリル

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