JPH0151076B2 - - Google Patents

Info

Publication number
JPH0151076B2
JPH0151076B2 JP13731786A JP13731786A JPH0151076B2 JP H0151076 B2 JPH0151076 B2 JP H0151076B2 JP 13731786 A JP13731786 A JP 13731786A JP 13731786 A JP13731786 A JP 13731786A JP H0151076 B2 JPH0151076 B2 JP H0151076B2
Authority
JP
Japan
Prior art keywords
film
etching
wiring
contact hole
layer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP13731786A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62295493A (ja
Inventor
Takeshi Myagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP13731786A priority Critical patent/JPS62295493A/ja
Publication of JPS62295493A publication Critical patent/JPS62295493A/ja
Publication of JPH0151076B2 publication Critical patent/JPH0151076B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
JP13731786A 1986-06-14 1986-06-14 高速素子実装用回路基板の製造方法 Granted JPS62295493A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13731786A JPS62295493A (ja) 1986-06-14 1986-06-14 高速素子実装用回路基板の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13731786A JPS62295493A (ja) 1986-06-14 1986-06-14 高速素子実装用回路基板の製造方法

Publications (2)

Publication Number Publication Date
JPS62295493A JPS62295493A (ja) 1987-12-22
JPH0151076B2 true JPH0151076B2 (de) 1989-11-01

Family

ID=15195856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13731786A Granted JPS62295493A (ja) 1986-06-14 1986-06-14 高速素子実装用回路基板の製造方法

Country Status (1)

Country Link
JP (1) JPS62295493A (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01150383A (ja) * 1987-12-07 1989-06-13 Mitsutoyo Corp パターン配線用電極体
JPH0728130B2 (ja) * 1987-12-07 1995-03-29 株式会社ミツトヨ 立体パターン配線構造およびその製造方法
JPH0298994A (ja) * 1988-10-06 1990-04-11 Ibiden Co Ltd ポリイミド絶縁層上への導体層形成方法
DE69105753T2 (de) * 1990-11-15 1995-05-24 Ibm Herstellungsmethode einer dünnschichtmehrlagenstruktur.
JP3166611B2 (ja) * 1996-04-19 2001-05-14 富士ゼロックス株式会社 プリント配線板及びその製造方法

Also Published As

Publication number Publication date
JPS62295493A (ja) 1987-12-22

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term