JPH0141032B2 - - Google Patents
Info
- Publication number
- JPH0141032B2 JPH0141032B2 JP57092737A JP9273782A JPH0141032B2 JP H0141032 B2 JPH0141032 B2 JP H0141032B2 JP 57092737 A JP57092737 A JP 57092737A JP 9273782 A JP9273782 A JP 9273782A JP H0141032 B2 JPH0141032 B2 JP H0141032B2
- Authority
- JP
- Japan
- Prior art keywords
- input
- terminals
- chip
- terminal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092737A JPS58209158A (ja) | 1982-05-31 | 1982-05-31 | マスタスライス半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57092737A JPS58209158A (ja) | 1982-05-31 | 1982-05-31 | マスタスライス半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58209158A JPS58209158A (ja) | 1983-12-06 |
| JPH0141032B2 true JPH0141032B2 (enrdf_load_stackoverflow) | 1989-09-01 |
Family
ID=14062725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57092737A Granted JPS58209158A (ja) | 1982-05-31 | 1982-05-31 | マスタスライス半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58209158A (enrdf_load_stackoverflow) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5941852A (ja) * | 1982-06-24 | 1984-03-08 | ストレイジ・テクノロジ−・パ−トナ−ズ | 集積回路チツプ |
| JPS59139646A (ja) * | 1983-01-31 | 1984-08-10 | Hitachi Micro Comput Eng Ltd | 半導体集積回路装置 |
| JPS59159557A (ja) * | 1983-03-01 | 1984-09-10 | Hitachi Ltd | 半導体集積回路装置 |
| JPS61204957A (ja) * | 1985-03-08 | 1986-09-11 | Hitachi Ltd | 大規模集積回路装置 |
| JPS61263241A (ja) * | 1985-05-17 | 1986-11-21 | Matsushita Electronics Corp | ゲ−トアレイ |
| JPH05308136A (ja) * | 1992-04-01 | 1993-11-19 | Nec Corp | マスタスライス集積回路 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5925381B2 (ja) * | 1977-12-30 | 1984-06-16 | 富士通株式会社 | 半導体集積回路装置 |
| JPS5561054A (en) * | 1978-10-30 | 1980-05-08 | Mitsubishi Electric Corp | Large scale integrated circuit |
| JPS58197746A (ja) * | 1982-05-14 | 1983-11-17 | Hitachi Ltd | 半導体集積回路装置 |
-
1982
- 1982-05-31 JP JP57092737A patent/JPS58209158A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58209158A (ja) | 1983-12-06 |