JPH0432545B2 - - Google Patents
Info
- Publication number
- JPH0432545B2 JPH0432545B2 JP61220154A JP22015486A JPH0432545B2 JP H0432545 B2 JPH0432545 B2 JP H0432545B2 JP 61220154 A JP61220154 A JP 61220154A JP 22015486 A JP22015486 A JP 22015486A JP H0432545 B2 JPH0432545 B2 JP H0432545B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- macrocell
- ground
- macro cell
- gnd
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/90—Masterslice integrated circuits
- H10D84/998—Input and output buffer/driver structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61220154A JPS6376345A (ja) | 1986-09-18 | 1986-09-18 | 出力マクロセルの構成方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61220154A JPS6376345A (ja) | 1986-09-18 | 1986-09-18 | 出力マクロセルの構成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6376345A JPS6376345A (ja) | 1988-04-06 |
JPH0432545B2 true JPH0432545B2 (enrdf_load_stackoverflow) | 1992-05-29 |
Family
ID=16746734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61220154A Granted JPS6376345A (ja) | 1986-09-18 | 1986-09-18 | 出力マクロセルの構成方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6376345A (enrdf_load_stackoverflow) |
-
1986
- 1986-09-18 JP JP61220154A patent/JPS6376345A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6376345A (ja) | 1988-04-06 |
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