JPS6376345A - 出力マクロセルの構成方法 - Google Patents

出力マクロセルの構成方法

Info

Publication number
JPS6376345A
JPS6376345A JP61220154A JP22015486A JPS6376345A JP S6376345 A JPS6376345 A JP S6376345A JP 61220154 A JP61220154 A JP 61220154A JP 22015486 A JP22015486 A JP 22015486A JP S6376345 A JPS6376345 A JP S6376345A
Authority
JP
Japan
Prior art keywords
output
macrocell
ground
macro cell
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61220154A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0432545B2 (enrdf_load_stackoverflow
Inventor
Akiyoshi Suzuki
鈴木　昭由
Keisuke Ishiwatari
石渡　啓介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61220154A priority Critical patent/JPS6376345A/ja
Publication of JPS6376345A publication Critical patent/JPS6376345A/ja
Publication of JPH0432545B2 publication Critical patent/JPH0432545B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/998—Input and output buffer/driver structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP61220154A 1986-09-18 1986-09-18 出力マクロセルの構成方法 Granted JPS6376345A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61220154A JPS6376345A (ja) 1986-09-18 1986-09-18 出力マクロセルの構成方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61220154A JPS6376345A (ja) 1986-09-18 1986-09-18 出力マクロセルの構成方法

Publications (2)

Publication Number Publication Date
JPS6376345A true JPS6376345A (ja) 1988-04-06
JPH0432545B2 JPH0432545B2 (enrdf_load_stackoverflow) 1992-05-29

Family

ID=16746734

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61220154A Granted JPS6376345A (ja) 1986-09-18 1986-09-18 出力マクロセルの構成方法

Country Status (1)

Country Link
JP (1) JPS6376345A (enrdf_load_stackoverflow)

Also Published As

Publication number Publication date
JPH0432545B2 (enrdf_load_stackoverflow) 1992-05-29

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