JPH0136702B2 - - Google Patents

Info

Publication number
JPH0136702B2
JPH0136702B2 JP57082583A JP8258382A JPH0136702B2 JP H0136702 B2 JPH0136702 B2 JP H0136702B2 JP 57082583 A JP57082583 A JP 57082583A JP 8258382 A JP8258382 A JP 8258382A JP H0136702 B2 JPH0136702 B2 JP H0136702B2
Authority
JP
Japan
Prior art keywords
lead member
solder
chip
semiconductor chip
piece
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP57082583A
Other languages
English (en)
Other versions
JPS58199534A (ja
Inventor
Shigemi Ono
Susumu Akyama
Shigeo Shimada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanken Electric Co Ltd
Original Assignee
Sanken Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanken Electric Co Ltd filed Critical Sanken Electric Co Ltd
Priority to JP57082583A priority Critical patent/JPS58199534A/ja
Publication of JPS58199534A publication Critical patent/JPS58199534A/ja
Publication of JPH0136702B2 publication Critical patent/JPH0136702B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
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Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 本発明は、整流素子等の半導体素子のリード部
材を量産性を有して接続する方法に関するもので
ある。
トランジスタやダイオードの内部リード部材の
接続はワイヤボンデイング法によつて一般に行わ
れている。しかし、ワイヤボンデイング法で使用
するボンダーは同時に１箇所しか接続できない。
また、太いリード線の接続には適していない。こ
の種の問題を解決するため、本願出願人は、特開
昭56―94754号公報に開示されている方法を提案
した。この方法によれば、電力用半導体素子の量
産化が可能になる。しかし、内部リードの半導体
チツプへのろう接、半導体チツプの基板へのろう
接、及び内部リードの外部リードへのろう接を独
立に行わなければならない。また、先にろう接し
た部分が後のろう接によつて悪影響を受けないよ
うにろう材を組み合せを工夫しなければならな
い。また、ろう材の組み合せを工夫してもろう接
の温度管理が不充分であれば、前のろう接部分が
劣化する恐れがあつた。更にリードフレームを使
用して例えばセンタータツプ型整流素子を製造す
る場合に、半導体チツプ部分を樹脂モールドした
後に、外部リードにPb―Sn共晶半田デツプ法等
で半田被覆を行うと、既にろう接されている部分
のろう材が再び融けるという問題が生じた。
上記欠点を解決するために、本願出願人は、特
願昭57―12123号で、第１図〜第３図に示す新規
な内部リード線の接続方法を提案した。この方法
では、まず、基板１及び外部リード部材２，３，
４を有する銅にニツケルメツキしたリードフレー
ムを用意する。また上下に電極を有するシリコン
ダイオードチツプ５を用意する。また銅にニツケ
ルメツキした外部リード部材接続用金属片６を用
意する。更に、Pb95重量％＋Sn5重量％から成る
固相線温度304℃、液相線温度314℃の半田片７，
８，９，１０を用意する。また、直径0.5mmのニ
ツケルメツキした銅線から成る丸棒状の内部リー
ド部材１１を用意する。
次に、カーボン製の治具にリードフレームをセ
ツトし、第１図に示す如く外部リード部材２の上
に半田片１０を介してデイスク状金属片６を配
し、この金属片６の上に半田片９を配す。次に、
基板１の上に半田片７を介してダイオードチツプ
５を配す。次に、チツプ５の上に半田片８を配
す。しかる後、丸棒状内部リード部材１１の一端
部１１ａをチツプ５の上に半田片８を介して配
し、またその他端部１１ｂを外部リード部材２の
上に半田片９，１０と金属片６とを介して配す。
金属片６はチツプ５と同じ厚さに形成されている
ので、内部リード部材１１はチツプ５の表面と同
一方向に伸びた状態即ち水平方向に伸びた状態と
なる。尚第１図には、センタタツプ整流素子の一
方のダイオード部分のみが示されているが、他方
のダイオード部分も同様に構成する。また、リー
ドフレームには多数の整流素子形成部分が設けら
れているので、同様に各部材を配す。
しかる後、第１図に示すものを、H2等の還元
性ガス又はN2等の不活性ガス雰囲気の加熱炉の
中に入れ、半田片７，８，９，１０を同時に融か
し、第２図に示す半田７ａ，８ａ，９ａ，１０ａ
によつて、基板１とチツプ５との間、チツプ５と
内部リード部材１１との間、内部リード部材１１
と外部リード部材の一部となる金属片６との間、
金属片６と外部リード部材２との間を同時にろう
接する。
次に、第３図で点線で示す部分を合成樹脂１２
でモールドする。また合成樹脂１２でモールドさ
れなかつた部分を半田浴に浸漬して外部リード部
材２，３，４を半田被覆する。またリードフレー
ムから外部リード部材２，３，４を分離する。
上述の如き方法によれば、合成樹脂１２でモー
ルドされる内部の各部分を同時にろう接すること
が可能になるので、量産性が大幅に向上する。ま
た各ろう接部分に融点の高いろう材を使用するこ
とが可能になるので、外部リード部材２，３，４
の露出部分を半田浸漬する場合等に於いて、内部
の半田が融けたり、軟化することが少なくなる。
しかし、リード線１１とチツプ５の側面との間に
半田８ａのたれた部分８ｂが生じ、PN接合の短
絡が生じることがあつた。
そこで、本発明の目的は、半田のたれを阻止し
て信頼性の高い半導体素子を量産することが可能
な内部リード部材の接続方法を提供することにあ
る。
上記目的を達成するための本発明は、導電性基
板の上にろう材片を介して半導体チツプを載置
し、棒状の内部リード部材の一端部を前記半導体
チツプの上に配し、前記内部リード部材の他端部
を外部リード部材の上に配し、前記内部リード部
材の一端部及び他端部の下又はその近傍にろう材
片を置き、且つ前記半導体チツプの表面と同一方
向に伸びるように前記内部リード部材を水平に保
持したものを加熱炉に入れ、前記基板と前記半導
体チツプとの間、前記半導体チツプと前記内部リ
ード部材との間、及び前記内部リード部材と前記
外部リード部材との間を同時にろう接する半導体
素子のリード部材の接続方法に於いて、前記内部
リード部材として少なくとも一端部に鍔状部を有
するものを使用し、前記鍔状部を前記半導体チツ
プの上面の縁から離れた前記上面の中央部上に配
置することを特徴とする半導体素子のリード部材
の接続方法に係わるものである。
上記発明によれば、内部リード部材として端部
に鍔状部を有するものを使用し、この鍔状部をチ
ツプ上面の中央部上に配置するのでリード部材の
水平に伸びる部分とチツプ上面との間に間隔が生
じ、溶融ろう材をこの部分に保持することが可能
になり、チツプ側面にろう材がたれるのを防止す
ることが可能になる。
次に、第４図〜第７図を参照して本発明の実施
例について述べる。但し、第４図〜第７図に於い
て符号１〜１２で示すものは第１図〜第３図で同
一符号で示すものと同一であるので、その説明を
省略する。
本実施例では、第４図に示す如く、内部リード
部材１１が直径約0.5mmの水平部分１３と先端に
於いて水平部分１３から半径方向に突出している
鍔状部分１４とで形成されている。尚鍔状部分１
４はリード部材１１の端を押しつぶすことによつ
て形成され、その最大径を約0.7mmとしたもので
ある。従つて水平部分１３と鍔状部分１４の最大
径周縁部との間に約0.1mmの段差が生じ、この段
差が半田片８の厚さ0.1mmと同程度に設定されて
いる。
第４図に示すように配置したものを加熱すれ
ば、半田片７，８，９，１０が溶融し、第５図に
示す如く半田７ａ，８ａ，９ａ，１０ａにて各部
が接着される。この際、内部リード部材１１には
鍔状部分１４が設けられているので、鍔状部分１
４の高さに相当した隙間が水平部分１３とチツプ
５の上面との間に生じ、半田８ａはこの隙間に保
持され、チツプ５の側面に殆んどたれない。ま
た、チツプ５の直径は約2.6〜３mmであり、この
中央部に第７図に示す鍔状部分１４を配すので、
水平部分１３に直交する面方向に於いても半田８
ａのたれが生じない。
従つて、本実施例によれば、第１図〜第３図と
同一の作用効果を得ることができるのみでなく、
半田８ａのたれを防止して歩留りを向上させるこ
とが可能になる。
以上、本発明の実施例について述べたが、本発
明はこれに限定されるものではなく、更に変形可
能なものである。例えば、第８図に示す如く、鍔
状部分１４を円板状に形成してもよい。またリー
ド部材１１の他端部１１ｂに大きな鍔状部分を設
け、これにより、金属片６を省く構成としてもよ
い。また鍔状部分１４の形状を外周縁が六角形等
の多角形となるようにしてもよい。また、近接さ
せて２つの鍔状部分１４を設け、いずれもチツプ
５上に置くようにしてもよい。また、リードフレ
ームを使用しない場合にも適用可能である。
【図面の簡単な説明】
第１図〜第３図は従来の整流素子の製造を示す
ものであり、第１図は整流素子の各部の配置を示
す第３図の―線に相当する断面図、第２図は
ろう接後の整流素子を示す断面図、第３図はリー
ドフレームから切断前の整流素子の平面図であ
る。第４図〜第７図は本発明の実施例に係わる整
流素子の製造を示すものであり、第４図は各部の
配置を示す第６図の―線に相当する部分の断
面図、第５図はろう接後の整流素子の断面図、第
６図はリードフレームの状態の平面図、第７図は
第４図の左側面の一部に相当する側面図である。
第８図は内部リード部材の変形例を示す正面図で
ある。 尚図面に用いられている符号に於いて、１は基
板、２，３，４は外部リード部材、５はダイオー
ドチツプ、６は金属片、７，８，９，１０は半田
片、１１は内部リード部材、１２は合成樹脂、１
３は水平部分、１４は鍔状部分である。

Claims (1)

  1. 【特許請求の範囲】 １ 導電性基板の上にろう材片を介して半導体チ
    ツプを載置し、棒状の内部リード部材の一端部を
    前記半導体チツプの上に配し、前記内部リード部
    材の他端部を外部リード部材の上に配し、前記内
    部リード部材の一端部及び他端部の下又はその近
    傍にろう材片を置き、且つ前記半導体チツプの表
    面と同一方向に伸びるように前記内部リード部材
    を水平に保持したものを加熱炉に入れ、前記基板
    と前記半導体チツプとの間、前記半導体チツプと
    前記内部リード部材との間、及び前記内部リード
    部材と前記外部リード部材との間を同時にろう接
    する半導体素子のリード部材の接続方法に於い
    て、 前記内部リード部材として少なくとも一端部に
    鍔状部を有するものを使用し、前記鍔状部を前記
    半導体チツプの上面の縁から離れた前記上面の中
    央部上に配置することを特徴とする半導体素子の
    リード部材の接続方法。
JP57082583A 1982-05-17 1982-05-17 半導体素子のリ−ド部材の接続方法 Granted JPS58199534A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57082583A JPS58199534A (ja) 1982-05-17 1982-05-17 半導体素子のリ−ド部材の接続方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57082583A JPS58199534A (ja) 1982-05-17 1982-05-17 半導体素子のリ−ド部材の接続方法

Publications (2)

Publication Number Publication Date
JPS58199534A JPS58199534A (ja) 1983-11-19
JPH0136702B2 true JPH0136702B2 (ja) 1989-08-02

Family

ID=13778498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57082583A Granted JPS58199534A (ja) 1982-05-17 1982-05-17 半導体素子のリ−ド部材の接続方法

Country Status (1)

Country Link
JP (1) JPS58199534A (ja)

Also Published As

Publication number Publication date
JPS58199534A (ja) 1983-11-19

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