JPH01255234A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPH01255234A
JPH01255234A JP63083802A JP8380288A JPH01255234A JP H01255234 A JPH01255234 A JP H01255234A JP 63083802 A JP63083802 A JP 63083802A JP 8380288 A JP8380288 A JP 8380288A JP H01255234 A JPH01255234 A JP H01255234A
Authority
JP
Japan
Prior art keywords
layer
semiconductor element
electrode pad
passivation film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63083802A
Other languages
English (en)
Other versions
JPH0533823B2 (ja
Inventor
Takashi Shibata
隆 柴田
Osamu Usuda
修 薄田
Isamu Wada
和田　勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63083802A priority Critical patent/JPH01255234A/ja
Publication of JPH01255234A publication Critical patent/JPH01255234A/ja
Publication of JPH0533823B2 publication Critical patent/JPH0533823B2/ja
Granted legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） この発明は半導体装置、特に銅系のワイヤをボンディン
グワイヤとして用いる半導体装置の電極の改良に関する
。
（従来の技術） トランジスタ、ダイオード等の個別半導体装置は、チッ
プ上の半導体素子をリードフレーム上にダイボンディン
グし、かつチップ上の電極パッドに対して金属ワイヤを
ボンディングすることにより配線される。
第２図（ａ）はワイヤボンディングが行われる前の従来
の半導体装置の断面図である。リードフレーム上Ｏ上に
半導体素子（チップ）　１１が接合されている。上記素
子ｌ【には絶縁膜Ｉ２が形成されており、この絶縁膜１
２の開口部にはアルミニウム層による電極パッド１３が
形成されている。さらにこの電極パッド１３の周辺上に
はリン争ケイ酸ガラス膜（ＰＳＧ膜）からなるパッシベ
ーション膜１４が形成されている。このような電極パッ
ド■３上に第２図（ｂ）に示すように例えば銅ワイヤ１
５がボンディングされる。
ところで、従来装置では電極パッド１３がアルミニウム
による層のみで構成されている。このため、ワイヤボン
ディング時の圧力により、パッド１３が変形し、銅ワイ
ヤが直接、素子１１に接合される恐れがある。このよう
な場合には、接合部における電気的特性の劣化、長時間
の使用による電気的特性の変動、等の致命的な不良が生
じる。
さらに、ワイヤボンディング時に位置ずれが生じ、銅ワ
イヤ１５がパッシベーション膜１４に乗った状態でボン
ディングが行われると、銅ワイヤ１５が硬いためにバッ
シベ〜ジョン膜１４が破壊されやすく、半導体素子１１
自体にダメージが発生してしまう。これは、パッシベー
ション膜■４を構成するリン・ケイ酸ガラス膜と半導体
素子１１を構成するシリコンとの線膨脹係数が異なって
いるためであり、このような構成では、熱サイクルを繰
返すことにより、半導体素子１１自体にダメージやクラ
ックが発生するという欠点がある。
（発明が解決しようとする課題） 従来の半導体装置の電極パッドの構成ではワイヤボンデ
ィング時の圧力により、電極パッドが変形して銅ワイヤ
が直接、半導体素子に接合される恐れがある。これによ
り、接合部における電気的特性の劣化、長時間の使用に
よる電気的特性の変動、等の致命的な不良が生じる欠点
がある。また、ワイヤボンディング時の位置ずれにより
、銅ワイヤがパッシベーション膜に乗った状態でボンデ
ィングが行われると、従来のパッシベーション膜では、
銅ワイヤによる破損が生じやすく、半導体素子自体にも
ダメージを与えやすい。従って、熱サイクルを繰返すこ
とにより、半導体素子自体にダメージやクラックが発生
するという欠点がある。
この発明は上記事情を考慮してなされたもので、その目
的は、ワイヤボンディング時に半導体素子にダメージを
与えない半導体装置を提供することにある。
［発明の構成］ （課題を解決するための手段） この発明の半導体装置は、半導体素子と、この半導体素
子上に形成され、第１層目がアルミニウム層もしくはア
ルミニウム合金層、第２層目がバナジウム層もしくはバ
ナジウム合金層あるいはチタン層もしくはチタン合金層
、第３層目がアルミニウム層もしくはアルミニウム合金
層で構成された電極パッドと、この電極パッド上に形成
され線膨脹係数が上記素子を構成する部材とほぼ等しい
部材で構成されたパッシベーション膜とから構成される
。
（作用） 半導体素子の電極を３層構造にすることにより、ワイヤ
ボンディング時において、３層目は銅ワイヤとの接合層
、２層目は銅ワイヤ接合時のダメージ防止層、１層目は
歪み緩和層として作用する。さらに、線膨脹係数を考慮
したパッシベーション膜は、ワイヤボンディング時の位
置ずれに対する半導体素子へのダメージ防止を図ってい
る。
（実施例） 以下、図面を参照してこの発明を実施例により説明する
。
第１図（ａ）はこの発明の半導体装置の断面図であり、
ワイヤボンディングが行われる前のちのである。リード
フレーム１上に半導体素子（チップ）２が接合されてい
る。上記素子２には絶縁膜３が形成されており、この絶
縁膜３の開口部には第１層目がアルミニウム層４、第２
層目がバナジウム層５、第３層目がアルミニウム層６で
構成された電極パッド７が形成されている。さらにこの
電極パッド７の周辺上にはシリコン窒化膜からなるバッ
シベーンヨン膜８が形成されている。
上記３層構造の電極パッド７は蒸着法により形成し、厚
さはそれぞれ、アルミニウム層４は０．３〜２．０μｍ
程度、バナジウム層５は０．１〜１μｍ程度、そして、
アルミニウム層６は０．５〜３．５μｍ程度に形成する
。一方、アルミニウム層６上のパッシベーション膜８（
シリコン窒化膜）はプラズマＣＶＤ　（化学気相成長）
法により、厚さ０，５〜１．６μｍ程度に形成する。こ
のような工程後、半導体素子ごとにカットした後、リー
ドフレーム１に接合する。
次に、上記電極パッド７上に第１図（ｂ）に示すように
例えば銅ワイヤ９がボンディングされる。
この工［呈では、上工己リードフレーム１を２００〜４
５０℃に加熱し、銅ワイヤ９が熱圧着もしくは超音波振
動により、電極パッド７と接合される。
このとき、図示のように最上層のアルミニウム層６は変
形するが、バナジウム層５はほとんど変形しない。しか
も、バナジウム層５下にはアルミニウム層３が一定厚さ
を維持しているので、接合時のダメージが緩和できる。
また、ワイヤボンディング時に位置ずれを起こしても、
パッシベーション膜８はシリコン窒化膜により形成され
、線膨脹係数がシリコンとほぼ同一であるので、耐熱、
耐衝撃性が従来のものより向上している。従って、半導
体素子２に与えるダメージは大幅に減少される。
上記発明の半導体装置を従来のものと比較したテスト結
果を述べる。同一条件で高温及び低温に対する熱サイク
ルテストを行った結果、従来の半導体装置では２００回
で約２０％が不良となり、さらに４００回では約４０％
が不良となったのに対し、この発明の半導体装置では４
００回でも不良が発生しなかった。一方、電極パッド７
と銅ワイヤ９を接合する際、ワイヤのボンディング位置
を正常位置から５０％ずらして接合した結果、従来の半
導体装置では２０〜５０％の電気的不良が発生したが、
この発明の半導体装置の不良発生率は０．１％以下であ
った。さらに、高温高湿放置１０００時間での電気的特
性不良発生率を比較した結果、従来の半導体装置では７
０％程度であるのに対し、この発明の半導体装置では０
．２％以下であった。
このように電極パッド７の構成をアルミニウム層４、バ
ナジウム層５、アルミニウム層６の３層構造にすること
によって、銅ワイヤ９接合時の半導体素子へのダメージ
の影響が大幅に減少する。
しかも、電気抵抗は従来のものと比べてほとんど変わら
ない。また、パッシベーション膜８を形成するシリコン
窒化膜は銅ワイヤ９のダメージ防止だけでなく、アルカ
リイオン等の外部汚染防止にも効果があるという利点が
ある。
なお、この発明は上記実施例に限定されるものではなく
種々の変形が可能であることはいうまでもない。上記実
施例ではアルミニウム層の間に形成する金属層としてバ
ナジウムを用いたが、この金属層はアルミニウムより硬
く、しかも電気抵抗に影響のないものであればよく、例
えばバナジウム合金、チタンもしくはチタン合金を用い
てもよい。また、パッシベーション膜８もシリコン窒化
膜に限定されるものではなく、例えば、炭化ケイ素や炭
化ジルコニウムにより形成してもよい。
［発明の効果］ 以上詳述したようにこの発明によれば、ワイヤボンディ
ングによるダメージが少ない半導体装置が提供できる。
【図面の簡単な説明】
第１図（ａ）及び（ｂ）はこの発明にかかる半導体装置
の断面図、第２図（ａ）及び（ｂ）は従来の半導体装置
の断面図である。 １・・・リードフレーム、２・・・半導体素子、３・・
・シリコン酸化膜、４．６・・・アルミニウム層、５・
・・バナジウム層、７・・・電極パッド、８・・・パッ
シベーション膜、９・・・銅ワイヤ。 出願人代理人　弁理士　鈴江武彦

Claims (1)

  1. 【特許請求の範囲】 　半導体素子と、 上記半導体素子上に形成され、第１層目がアルミニウム
    層もしくはアルミニウム合金層、第２層目がバナジウム
    層もしくはバナジウム合金層あるいはチタン層もしくは
    チタン合金層、第３層目がアルミニウム層もしくはアル
    ミニウム合金層で構成された電極パッドと、 上記電極パッド上に形成され線膨脹係数が上記素子を構
    成する部材とほぼ等しい部材で構成されたパッシベーシ
    ョン膜と を具備したことを特徴とする半導体装置。
JP63083802A 1988-04-05 1988-04-05 半導体装置 Granted JPH01255234A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63083802A JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63083802A JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Publications (2)

Publication Number Publication Date
JPH01255234A true JPH01255234A (ja) 1989-10-12
JPH0533823B2 JPH0533823B2 (ja) 1993-05-20

Family

ID=13812792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63083802A Granted JPH01255234A (ja) 1988-04-05 1988-04-05 半導体装置

Country Status (1)

Country Link
JP (1) JPH01255234A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2362510B (en) * 1999-12-20 2003-07-02 Lucent Technologies Inc Wire bonding method for copper interconnects in semiconductor devices
DE102006044691A1 (de) * 2006-09-22 2008-03-27 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
JP2010258286A (ja) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2013089630A (ja) * 2011-10-13 2013-05-13 Hitachi Chemical Co Ltd 半導体パッケージ及びその製造方法
JP2014021065A (ja) * 2012-07-23 2014-02-03 Denso Corp 物理量センサ

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212169A (ja) * 1982-06-04 1983-12-09 Toshiba Corp 三層電極構造を有する半導体装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58212169A (ja) * 1982-06-04 1983-12-09 Toshiba Corp 三層電極構造を有する半導体装置

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2362510B (en) * 1999-12-20 2003-07-02 Lucent Technologies Inc Wire bonding method for copper interconnects in semiconductor devices
US6790757B1 (en) 1999-12-20 2004-09-14 Agere Systems Inc. Wire bonding method for copper interconnects in semiconductor devices
DE102006044691A1 (de) * 2006-09-22 2008-03-27 Infineon Technologies Ag Elektronisches Bauteil und Verfahren zum Herstellen
US8076238B2 (en) 2006-09-22 2011-12-13 Infineon Technologies Ag Electronic device and method for production
DE102006044691B4 (de) * 2006-09-22 2012-06-21 Infineon Technologies Ag Verfahren zum Herstellen einer Anschlussleitstruktur eines Bauelements
US8552571B2 (en) 2006-09-22 2013-10-08 Infineon Technologies Ag Electronic device and method for production
US9368447B2 (en) 2006-09-22 2016-06-14 Infineon Technologies Ag Electronic device and method for production
US9754912B2 (en) 2006-09-22 2017-09-05 Infineon Technologies Ag Electronic device and method for production
JP2010258286A (ja) * 2009-04-27 2010-11-11 Sanyo Electric Co Ltd 半導体装置及びその製造方法
JP2013089630A (ja) * 2011-10-13 2013-05-13 Hitachi Chemical Co Ltd 半導体パッケージ及びその製造方法
JP2014021065A (ja) * 2012-07-23 2014-02-03 Denso Corp 物理量センサ

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