JP7775536B2 - Ｓｒａｍセル構造 - Google Patents

Ｓｒａｍセル構造

Info

Publication number
JP7775536B2
JP7775536B2 JP2022033746A JP2022033746A JP7775536B2 JP 7775536 B2 JP7775536 B2 JP 7775536B2 JP 2022033746 A JP2022033746 A JP 2022033746A JP 2022033746 A JP2022033746 A JP 2022033746A JP 7775536 B2 JP7775536 B2 JP 7775536B2
Authority
JP
Japan
Prior art keywords
layer
metal
region
transistors
sram cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2022033746A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022140348A5 (enExample
JP2022140348A (ja
Inventor
チュン ル チャオ
ピン ファン リ
イン チュエ ジャン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Etron Technology Inc
Original Assignee
Etron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Etron Technology Inc filed Critical Etron Technology Inc
Publication of JP2022140348A publication Critical patent/JP2022140348A/ja
Publication of JP2022140348A5 publication Critical patent/JP2022140348A5/ja
Application granted granted Critical
Publication of JP7775536B2 publication Critical patent/JP7775536B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/18—Peripheral circuit regions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Hall/Mr Elements (AREA)
JP2022033746A 2021-03-10 2022-03-04 Ｓｒａｍセル構造 Active JP7775536B2 (ja)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US202163158896P 2021-03-10 2021-03-10
US63/158,896 2021-03-10
US202163162569P 2021-03-18 2021-03-18
US63/162,569 2021-03-18
US17/395,922 2021-08-06
US17/395,922 US20220302129A1 (en) 2021-03-10 2021-08-06 SRAM Cell Structures

Publications (3)

Publication Number Publication Date
JP2022140348A JP2022140348A (ja) 2022-09-26
JP2022140348A5 JP2022140348A5 (enExample) 2024-07-31
JP7775536B2 true JP7775536B2 (ja) 2025-11-26

Family

ID=80683041

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022033746A Active JP7775536B2 (ja) 2021-03-10 2022-03-04 Ｓｒａｍセル構造

Country Status (6)

Country Link
US (1) US20220302129A1 (enExample)
EP (1) EP4057348A3 (enExample)
JP (1) JP7775536B2 (enExample)
KR (2) KR20220129692A (enExample)
CN (1) CN115083472A (enExample)
TW (2) TWI843480B (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW202327047A (zh) * 2021-12-16 2023-07-01 新加坡商發明與合作實驗室有限公司 高性能運算和高儲存容量的同構/異構積體電路系統
US12334178B2 (en) 2023-01-27 2025-06-17 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit, system and method of forming the same
US20240304624A1 (en) * 2023-03-10 2024-09-12 Invention And Collaboration Laboratory, Inc. metal-oxide-semiconductor transistor and complementary metal-oxide-semiconductor circuit related

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103862A (ja) 2005-10-07 2007-04-19 Renesas Technology Corp 半導体装置およびその製造方法
US20130242645A1 (en) 2010-07-20 2013-09-19 University Of Virginia Patent Foundation Memory Cell
US20200168736A1 (en) 2018-11-26 2020-05-28 Etron Technology, Inc. Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof
WO2020167393A1 (en) 2019-02-11 2020-08-20 Applied Materials, Inc. Gate contact over active processes

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US5338698A (en) * 1992-12-18 1994-08-16 International Business Machines Corporation Method of fabricating an ultra-short channel field effect transistor
JP2684979B2 (ja) * 1993-12-22 1997-12-03 日本電気株式会社 半導体集積回路装置及びその製造方法
AU5901899A (en) * 1998-08-25 2000-03-14 Micron Technology, Inc. Method and structure for improved alignment tolerance in multiple, singularized plugs
JP4565700B2 (ja) * 1999-05-12 2010-10-20 ルネサスエレクトロニクス株式会社 半導体装置
JP3519662B2 (ja) * 2000-03-14 2004-04-19 松下電器産業株式会社 半導体装置及びその製造方法
SG115742A1 (en) * 2004-04-05 2005-10-28 Taiwan Semiconductor Mfg Sram device having high aspect ratio cell boundary
US8288813B2 (en) * 2004-08-13 2012-10-16 Infineon Technologies Ag Integrated memory device having columns having multiple bit lines
JP2006165480A (ja) * 2004-12-10 2006-06-22 Toshiba Corp 半導体装置
WO2009095998A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置
KR101567024B1 (ko) * 2009-05-15 2015-11-09 삼성전자주식회사 반도체 기억 소자
ES2785075T3 (es) * 2009-07-30 2020-10-05 Qualcomm Inc Sistemas en paquetes
JP5829611B2 (ja) * 2009-09-30 2015-12-09 三重富士通セミコンダクター株式会社 電界効果トランジスタ及びその製造方法
US8273617B2 (en) * 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8436404B2 (en) * 2009-12-30 2013-05-07 Intel Corporation Self-aligned contacts
US9875788B2 (en) * 2010-03-25 2018-01-23 Qualcomm Incorporated Low-power 5T SRAM with improved stability and reduced bitcell size
US8455932B2 (en) * 2011-05-06 2013-06-04 International Business Machines Corporation Local interconnect structure self-aligned to gate structure
US10181474B2 (en) * 2011-09-19 2019-01-15 Texas Instruments Incorporated SRAM layout for double patterning
US9048136B2 (en) * 2011-10-26 2015-06-02 GlobalFoundries, Inc. SRAM cell with individual electrical device threshold control
US9006841B2 (en) * 2011-12-30 2015-04-14 Stmicroelectronics International N.V. Dual port SRAM having reduced cell size and rectangular shape
US9036404B2 (en) * 2012-03-30 2015-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for SRAM cell structure
US20150325514A1 (en) * 2014-05-09 2015-11-12 Qualcomm Incorporated High density sram array design with skipped, inter-layer conductive contacts
US9318564B2 (en) * 2014-05-19 2016-04-19 Qualcomm Incorporated High density static random access memory array having advanced metal patterning
KR102310122B1 (ko) * 2014-06-10 2021-10-08 삼성전자주식회사 논리 셀 및 이를 포함하는 집적회로 소자와 논리 셀의 제조 방법 및 집적회로 소자의 제조 방법
US9515077B1 (en) * 2015-12-18 2016-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Layout of static random access memory cell
JP2017138918A (ja) 2016-02-05 2017-08-10 ヤマハ株式会社 コンテンツ表示制御方法、プログラム、及びコンテンツ表示制御装置
US9646974B1 (en) * 2016-03-25 2017-05-09 Taiwan Semiconductor Manufacturing Co., Ltd. Dual-port static random access memory
US10461086B2 (en) * 2016-10-31 2019-10-29 Taiwan Semiconductor Manufacturing Co., Ltd. Memory cell structure
KR102343202B1 (ko) * 2017-06-20 2021-12-23 삼성전자주식회사 반도체 장치 및 이의 제조 방법
US10867864B2 (en) * 2018-09-27 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10763863B2 (en) * 2018-09-28 2020-09-01 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device for logic and memory co-optimization
US11973120B2 (en) * 2020-06-24 2024-04-30 Etron Technology, Inc. Miniaturized transistor structure with controlled dimensions of source/drain and contact-opening and related manufacture method
KR102890789B1 (ko) * 2020-08-18 2025-11-27 삼성전자주식회사 반도체 장치
US12501600B2 (en) * 2021-10-04 2025-12-16 Invention And Collaboration Laboratory Pte. Ltd. SRAM cell structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007103862A (ja) 2005-10-07 2007-04-19 Renesas Technology Corp 半導体装置およびその製造方法
US20130242645A1 (en) 2010-07-20 2013-09-19 University Of Virginia Patent Foundation Memory Cell
US20200168736A1 (en) 2018-11-26 2020-05-28 Etron Technology, Inc. Reduced-form-factor transistor with self-aligned terminals and adjustable on/off-currents and manufacture method thereof
WO2020167393A1 (en) 2019-02-11 2020-08-20 Applied Materials, Inc. Gate contact over active processes

Also Published As

Publication number Publication date
KR20220129692A (ko) 2022-09-23
US20220302129A1 (en) 2022-09-22
TW202238591A (zh) 2022-10-01
TWI843480B (zh) 2024-05-21
EP4057348A3 (en) 2023-01-04
KR20250047958A (ko) 2025-04-07
CN115083472A (zh) 2022-09-20
JP2022140348A (ja) 2022-09-26
TW202329109A (zh) 2023-07-16
TWI801162B (zh) 2023-05-01
EP4057348A2 (en) 2022-09-14

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