JP7504035B2 - スーパーストレート及びその製造方法 - Google Patents

スーパーストレート及びその製造方法 Download PDF

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Publication number
JP7504035B2
JP7504035B2 JP2021003721A JP2021003721A JP7504035B2 JP 7504035 B2 JP7504035 B2 JP 7504035B2 JP 2021003721 A JP2021003721 A JP 2021003721A JP 2021003721 A JP2021003721 A JP 2021003721A JP 7504035 B2 JP7504035 B2 JP 7504035B2
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Japan
Prior art keywords
superstrate
blank
superstraight
coating
microns
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JP2021003721A
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English (en)
Japanese (ja)
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JP2021160352A5 (enExample
JP2021160352A (ja
Inventor
ワン フェン
リウ ウェイジュン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
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Canon Inc
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Publication of JP2021160352A publication Critical patent/JP2021160352A/ja
Publication of JP2021160352A5 publication Critical patent/JP2021160352A5/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/6715—Apparatus for applying a liquid, a resin, an ink or the like
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0015—Production of aperture devices, microporous systems or stamps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
    • H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
    • H01L21/68757—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a coating or a hardness or a material
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B05—SPRAYING OR ATOMISING IN GENERAL; APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D—PROCESSES FOR APPLYING FLUENT MATERIALS TO SURFACES, IN GENERAL
    • B05D1/00—Processes for applying liquids or other fluent materials
    • B05D1/002—Processes for applying liquids or other fluent materials the substrate being rotated
    • B05D1/005—Spin coating
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76804—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics by forming tapered via holes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Application Of Or Painting With Fluid Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2021003721A 2020-03-30 2021-01-13 スーパーストレート及びその製造方法 Active JP7504035B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/834,465 US12136564B2 (en) 2020-03-30 2020-03-30 Superstrate and method of making it
US16/834,465 2020-03-30

Publications (3)

Publication Number Publication Date
JP2021160352A JP2021160352A (ja) 2021-10-11
JP2021160352A5 JP2021160352A5 (enExample) 2023-10-17
JP7504035B2 true JP7504035B2 (ja) 2024-06-21

Family

ID=77854686

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021003721A Active JP7504035B2 (ja) 2020-03-30 2021-01-13 スーパーストレート及びその製造方法

Country Status (5)

Country Link
US (1) US12136564B2 (enExample)
JP (1) JP7504035B2 (enExample)
KR (1) KR20210122100A (enExample)
CN (1) CN113471101B (enExample)
TW (1) TWI834943B (enExample)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11562924B2 (en) * 2020-01-31 2023-01-24 Canon Kabushiki Kaisha Planarization apparatus, planarization process, and method of manufacturing an article
US12325046B2 (en) * 2022-06-28 2025-06-10 Canon Kabushiki Kaisha Superstrate including a body and layers and methods of forming and using the same
US11878935B1 (en) * 2022-12-27 2024-01-23 Canon Kabushiki Kaisha Method of coating a superstrate
US20240411225A1 (en) * 2023-06-09 2024-12-12 Canon Kabushiki Kaisha System including heating means and actinic radiation source and a method of using the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014204068A (ja) 2013-04-09 2014-10-27 パナソニック株式会社 微細構造体、その製造方法、及び微細構造金型
JP2015170828A (ja) 2014-03-11 2015-09-28 富士フイルム株式会社 プラズマエッチング方法およびパターン化基板の製造方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3918221B2 (ja) 1997-03-12 2007-05-23 ソニー株式会社 保護膜形成装置及び保護膜形成方法
US6140254A (en) 1998-09-18 2000-10-31 Alliedsignal Inc. Edge bead removal for nanoporous dielectric silica coatings
US20080160129A1 (en) * 2006-05-11 2008-07-03 Molecular Imprints, Inc. Template Having a Varying Thickness to Facilitate Expelling a Gas Positioned Between a Substrate and the Template
JP5456465B2 (ja) 2007-06-04 2014-03-26 丸善石油化学株式会社 微細加工品およびその製造方法
JP4609562B2 (ja) * 2008-09-10 2011-01-12 日立電線株式会社 微細構造転写用スタンパ及びその製造方法
RU2449415C1 (ru) * 2010-10-25 2012-04-27 Российская Федерация, От Имени Которой Выступает Министерство Промышленности И Торговли Российской Федерации Способ изготовления высоковольтного силового полупроводникового прибора
US10354858B2 (en) 2013-12-31 2019-07-16 Texas Instruments Incorporated Process for forming PZT or PLZT thinfilms with low defectivity
JP6385131B2 (ja) * 2014-05-13 2018-09-05 株式会社ディスコ ウェーハの加工方法
JP2017010962A (ja) * 2015-06-16 2017-01-12 株式会社東芝 デバイス基板およびデバイス基板の製造方法並びに半導体装置の製造方法
JP6649600B2 (ja) 2015-08-03 2020-02-19 三菱自動車工業株式会社 電動車両の回生制御装置
JP7065076B2 (ja) 2016-08-12 2022-05-11 インプリア・コーポレイション 金属含有レジストからのエッジビード領域における金属残留物を低減する方法
JP2019016616A (ja) * 2017-07-03 2019-01-31 大日本印刷株式会社 インプリントモールド及びその製造方法、並びに配線基板の製造方法
JP7258906B2 (ja) 2018-03-15 2023-04-17 アプライド マテリアルズ インコーポレイテッド 半導体素子パッケージ製造プロセスための平坦化
US11137536B2 (en) * 2018-07-26 2021-10-05 Facebook Technologies, Llc Bragg-like gratings on high refractive index material
KR102810856B1 (ko) * 2019-09-02 2025-05-20 삼성전자주식회사 반도체 소자 제조 장치, 반도체 소자 검사 장치 및 반도체 소자 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014204068A (ja) 2013-04-09 2014-10-27 パナソニック株式会社 微細構造体、その製造方法、及び微細構造金型
JP2015170828A (ja) 2014-03-11 2015-09-28 富士フイルム株式会社 プラズマエッチング方法およびパターン化基板の製造方法

Also Published As

Publication number Publication date
CN113471101A (zh) 2021-10-01
TW202136013A (zh) 2021-10-01
US20210305082A1 (en) 2021-09-30
KR20210122100A (ko) 2021-10-08
CN113471101B (zh) 2025-10-28
US12136564B2 (en) 2024-11-05
JP2021160352A (ja) 2021-10-11
TWI834943B (zh) 2024-03-11

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