JP7465200B2 - 遅延回路 - Google Patents

遅延回路 Download PDF

Info

Publication number
JP7465200B2
JP7465200B2 JP2020190639A JP2020190639A JP7465200B2 JP 7465200 B2 JP7465200 B2 JP 7465200B2 JP 2020190639 A JP2020190639 A JP 2020190639A JP 2020190639 A JP2020190639 A JP 2020190639A JP 7465200 B2 JP7465200 B2 JP 7465200B2
Authority
JP
Japan
Prior art keywords
transistor
drain
power supply
delay circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2020190639A
Other languages
English (en)
Japanese (ja)
Other versions
JP2022079823A5 (enExample
JP2022079823A (ja
Inventor
茂行 岡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Ablic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ablic Inc filed Critical Ablic Inc
Priority to JP2020190639A priority Critical patent/JP7465200B2/ja
Priority to KR1020210142545A priority patent/KR102845796B1/ko
Priority to CN202111261435.8A priority patent/CN114513197B/zh
Priority to US17/516,726 priority patent/US11437984B2/en
Priority to TW110141535A priority patent/TWI854165B/zh
Priority to EP21207676.4A priority patent/EP4002690B1/en
Publication of JP2022079823A publication Critical patent/JP2022079823A/ja
Publication of JP2022079823A5 publication Critical patent/JP2022079823A5/ja
Application granted granted Critical
Publication of JP7465200B2 publication Critical patent/JP7465200B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
JP2020190639A 2020-11-17 2020-11-17 遅延回路 Active JP7465200B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路
KR1020210142545A KR102845796B1 (ko) 2020-11-17 2021-10-25 지연 회로
CN202111261435.8A CN114513197B (zh) 2020-11-17 2021-10-28 延迟电路
US17/516,726 US11437984B2 (en) 2020-11-17 2021-11-02 Delay circuit
TW110141535A TWI854165B (zh) 2020-11-17 2021-11-08 延遲電路
EP21207676.4A EP4002690B1 (en) 2020-11-17 2021-11-11 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路

Publications (3)

Publication Number Publication Date
JP2022079823A JP2022079823A (ja) 2022-05-27
JP2022079823A5 JP2022079823A5 (enExample) 2023-04-26
JP7465200B2 true JP7465200B2 (ja) 2024-04-10

Family

ID=78598891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020190639A Active JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路

Country Status (6)

Country Link
US (1) US11437984B2 (enExample)
EP (1) EP4002690B1 (enExample)
JP (1) JP7465200B2 (enExample)
KR (1) KR102845796B1 (enExample)
CN (1) CN114513197B (enExample)
TW (1) TWI854165B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102480273B1 (ko) * 2020-12-03 2022-12-23 주식회사 지2터치 Ｐ형 트랜지스터를 포함하는 프로그램 가능한 전압이 인가되는 터치 스크린

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124858A (ja) 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
JP2003273712A (ja) 2002-03-15 2003-09-26 Nec Electronics Corp 遅延回路と半導体記憶装置及び遅延方法と半導体記憶装置の制御方法

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179539A (en) * 1988-05-25 1993-01-12 Hitachi, Ltd., Hitachi Vlsi Engineering Corporation Large scale integrated circuit having low internal operating voltage
JPH05110396A (ja) * 1991-10-16 1993-04-30 Olympus Optical Co Ltd 信号遅延回路
JPH05304464A (ja) * 1992-04-27 1993-11-16 Nec Ic Microcomput Syst Ltd 入力バッファ回路
KR100331257B1 (ko) * 1998-06-30 2002-08-21 주식회사 하이닉스반도체 일정한지연을갖는지연회로
JP2001210093A (ja) * 2000-01-25 2001-08-03 Mitsubishi Electric Corp リペア信号発生回路
KR100399595B1 (ko) * 2000-11-23 2003-09-26 삼성전자주식회사 신호 지연회로 및 이 회로를 이용한 반도체 메모리 장치
KR20040014839A (ko) * 2002-08-12 2004-02-18 삼성전자주식회사 온도 변화에 따른 지연 시간의 변화를 감소시키는 지연회로
US7619457B1 (en) * 2006-01-20 2009-11-17 Marvell International Ltd. Programmable delay circuit
JP4971699B2 (ja) * 2006-06-26 2012-07-11 ルネサスエレクトロニクス株式会社 遅延回路
CN101123426A (zh) * 2006-08-10 2008-02-13 普诚科技股份有限公司 延迟电路
US7557631B2 (en) * 2006-11-07 2009-07-07 Micron Technology, Inc. Voltage and temperature compensation delay system and method
US7932764B2 (en) * 2007-12-06 2011-04-26 Elite Semiconductor Memory Technology Inc. Delay circuit with constant time delay independent of temperature variations
KR100948076B1 (ko) 2008-04-14 2010-03-16 주식회사 하이닉스반도체 지연회로 및 이를 포함하는 반도체 메모리장치
US7944262B2 (en) * 2008-05-21 2011-05-17 Elpida Memory, Inc. Duty correction circuit
JP5195547B2 (ja) 2009-03-13 2013-05-08 富士電機株式会社 半導体装置
CN101557213B (zh) * 2009-03-27 2011-12-21 华为技术有限公司 延迟单元、环形振荡器及pll电路
US20100327902A1 (en) * 2009-06-25 2010-12-30 Uniram Technology, Inc. Power saving termination circuits for dram modules
TW201317551A (zh) * 2011-10-19 2013-05-01 Ili Technology Corp 溫度感測裝置
JP2013110661A (ja) 2011-11-24 2013-06-06 Elpida Memory Inc 半導体装置
US8624652B1 (en) * 2012-07-02 2014-01-07 Sandisk Technologies Inc. Accurate low-power delay circuit
KR20140062997A (ko) * 2012-11-15 2014-05-27 삼성전기주식회사 역률 보정 장치, 이를 갖는 전원 공급 장치 및 모터 구동 장치
US9401612B2 (en) * 2014-09-16 2016-07-26 Navitas Semiconductor Inc. Pulsed level shift and inverter circuits for GaN devices
WO2016065504A1 (en) 2014-10-27 2016-05-06 Texas Instruments Incorporated Dc-dc converter with temperature, process and voltage compensated dead time delay
US10110221B1 (en) * 2018-02-21 2018-10-23 Navitas Semiconductor, Inc. Power transistor control signal gating

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124858A (ja) 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
JP2003273712A (ja) 2002-03-15 2003-09-26 Nec Electronics Corp 遅延回路と半導体記憶装置及び遅延方法と半導体記憶装置の制御方法

Also Published As

Publication number Publication date
KR20220067490A (ko) 2022-05-24
CN114513197B (zh) 2025-09-19
US20220158630A1 (en) 2022-05-19
EP4002690A1 (en) 2022-05-25
EP4002690B1 (en) 2025-10-29
CN114513197A (zh) 2022-05-17
TWI854165B (zh) 2024-09-01
US11437984B2 (en) 2022-09-06
TW202222037A (zh) 2022-06-01
KR102845796B1 (ko) 2025-08-13
JP2022079823A (ja) 2022-05-27

Similar Documents

Publication Publication Date Title
US6064227A (en) Output buffer circuit having low breakdown voltage
US7317335B2 (en) Level shifter with low leakage current
US8154323B2 (en) Output driver operable over wide range of voltages
US11362660B2 (en) Level shifter circuit and method of operating the same
US9136827B2 (en) Power-on reset circuit
TWI674720B (zh) 電源保護電路
US20090230998A1 (en) Driver circuit
US7750723B2 (en) Voltage generation circuit provided in a semiconductor integrated device
JP3948621B2 (ja) インターフェース回路
JPH0865135A (ja) 出力バッファ回路
US10958267B2 (en) Power-on clear circuit and semiconductor device
US6753707B2 (en) Delay circuit and semiconductor device using the same
JP7465200B2 (ja) 遅延回路
US7218145B2 (en) Level conversion circuit
TWI641219B (zh) 電源啟動控制電路以及輸入／出控制電路
US7514960B2 (en) Level shifter circuit
US11075626B2 (en) Power-on clear circuit and semiconductor device
JP4192793B2 (ja) 半導体集積回路及びパワーオンリセット回路
US7642818B1 (en) High voltage tolerant input circuit capable of operating at extremely low IO supply voltage
JPH11326398A (ja) 電圧検知回路
JPH02134862A (ja) 半導体集積回路装置
US8629696B2 (en) Semiconductor device and level shifting circuit for the same
JP2003152518A (ja) 電圧供給回路
JP2008148024A (ja) リセット回路
JP2002335148A (ja) パワーオンリセット回路

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20230418

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230418

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20231013

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20231024

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231212

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240312

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240329

R150 Certificate of patent or registration of utility model

Ref document number: 7465200

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150