JP2022079823A5 - - Google Patents

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Publication number
JP2022079823A5
JP2022079823A5 JP2020190639A JP2020190639A JP2022079823A5 JP 2022079823 A5 JP2022079823 A5 JP 2022079823A5 JP 2020190639 A JP2020190639 A JP 2020190639A JP 2020190639 A JP2020190639 A JP 2020190639A JP 2022079823 A5 JP2022079823 A5 JP 2022079823A5
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JP
Japan
Prior art keywords
transistor
pmos transistor
delay circuit
level
voltage
Prior art date
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Application number
JP2020190639A
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English (en)
Japanese (ja)
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JP7465200B2 (ja
JP2022079823A (ja
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Publication date
Application filed filed Critical
Priority claimed from JP2020190639A external-priority patent/JP7465200B2/ja
Priority to JP2020190639A priority Critical patent/JP7465200B2/ja
Priority to KR1020210142545A priority patent/KR102845796B1/ko
Priority to CN202111261435.8A priority patent/CN114513197B/zh
Priority to US17/516,726 priority patent/US11437984B2/en
Priority to TW110141535A priority patent/TWI854165B/zh
Priority to EP21207676.4A priority patent/EP4002690B1/en
Publication of JP2022079823A publication Critical patent/JP2022079823A/ja
Publication of JP2022079823A5 publication Critical patent/JP2022079823A5/ja
Publication of JP7465200B2 publication Critical patent/JP7465200B2/ja
Application granted granted Critical
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2020190639A 2020-11-17 2020-11-17 遅延回路 Active JP7465200B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路
KR1020210142545A KR102845796B1 (ko) 2020-11-17 2021-10-25 지연 회로
CN202111261435.8A CN114513197B (zh) 2020-11-17 2021-10-28 延迟电路
US17/516,726 US11437984B2 (en) 2020-11-17 2021-11-02 Delay circuit
TW110141535A TWI854165B (zh) 2020-11-17 2021-11-08 延遲電路
EP21207676.4A EP4002690B1 (en) 2020-11-17 2021-11-11 Delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路

Publications (3)

Publication Number Publication Date
JP2022079823A JP2022079823A (ja) 2022-05-27
JP2022079823A5 true JP2022079823A5 (enExample) 2023-04-26
JP7465200B2 JP7465200B2 (ja) 2024-04-10

Family

ID=78598891

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020190639A Active JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路

Country Status (6)

Country Link
US (1) US11437984B2 (enExample)
EP (1) EP4002690B1 (enExample)
JP (1) JP7465200B2 (enExample)
KR (1) KR102845796B1 (enExample)
CN (1) CN114513197B (enExample)
TW (1) TWI854165B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102480273B1 (ko) * 2020-12-03 2022-12-23 주식회사 지2터치 Ｐ형 트랜지스터를 포함하는 프로그램 가능한 전압이 인가되는 터치 스크린

Family Cites Families (26)

* Cited by examiner, † Cited by third party
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US5179539A (en) * 1988-05-25 1993-01-12 Hitachi, Ltd., Hitachi Vlsi Engineering Corporation Large scale integrated circuit having low internal operating voltage
JPH05110396A (ja) * 1991-10-16 1993-04-30 Olympus Optical Co Ltd 信号遅延回路
JPH05304464A (ja) * 1992-04-27 1993-11-16 Nec Ic Microcomput Syst Ltd 入力バッファ回路
KR100331257B1 (ko) * 1998-06-30 2002-08-21 주식회사 하이닉스반도체 일정한지연을갖는지연회로
JP2001210093A (ja) * 2000-01-25 2001-08-03 Mitsubishi Electric Corp リペア信号発生回路
JP2002124858A (ja) * 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
KR100399595B1 (ko) * 2000-11-23 2003-09-26 삼성전자주식회사 신호 지연회로 및 이 회로를 이용한 반도체 메모리 장치
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
KR20040014839A (ko) * 2002-08-12 2004-02-18 삼성전자주식회사 온도 변화에 따른 지연 시간의 변화를 감소시키는 지연회로
US7619457B1 (en) * 2006-01-20 2009-11-17 Marvell International Ltd. Programmable delay circuit
JP4971699B2 (ja) * 2006-06-26 2012-07-11 ルネサスエレクトロニクス株式会社 遅延回路
CN101123426A (zh) * 2006-08-10 2008-02-13 普诚科技股份有限公司 延迟电路
US7557631B2 (en) * 2006-11-07 2009-07-07 Micron Technology, Inc. Voltage and temperature compensation delay system and method
US7932764B2 (en) * 2007-12-06 2011-04-26 Elite Semiconductor Memory Technology Inc. Delay circuit with constant time delay independent of temperature variations
KR100948076B1 (ko) 2008-04-14 2010-03-16 주식회사 하이닉스반도체 지연회로 및 이를 포함하는 반도체 메모리장치
US7944262B2 (en) * 2008-05-21 2011-05-17 Elpida Memory, Inc. Duty correction circuit
JP5195547B2 (ja) 2009-03-13 2013-05-08 富士電機株式会社 半導体装置
CN101557213B (zh) * 2009-03-27 2011-12-21 华为技术有限公司 延迟单元、环形振荡器及pll电路
US20100327902A1 (en) * 2009-06-25 2010-12-30 Uniram Technology, Inc. Power saving termination circuits for dram modules
TW201317551A (zh) * 2011-10-19 2013-05-01 Ili Technology Corp 溫度感測裝置
JP2013110661A (ja) 2011-11-24 2013-06-06 Elpida Memory Inc 半導体装置
US8624652B1 (en) * 2012-07-02 2014-01-07 Sandisk Technologies Inc. Accurate low-power delay circuit
KR20140062997A (ko) * 2012-11-15 2014-05-27 삼성전기주식회사 역률 보정 장치, 이를 갖는 전원 공급 장치 및 모터 구동 장치
US9401612B2 (en) * 2014-09-16 2016-07-26 Navitas Semiconductor Inc. Pulsed level shift and inverter circuits for GaN devices
WO2016065504A1 (en) 2014-10-27 2016-05-06 Texas Instruments Incorporated Dc-dc converter with temperature, process and voltage compensated dead time delay
US10110221B1 (en) * 2018-02-21 2018-10-23 Navitas Semiconductor, Inc. Power transistor control signal gating

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