KR102845796B1 - 지연 회로 - Google Patents

지연 회로

Info

Publication number
KR102845796B1
KR102845796B1 KR1020210142545A KR20210142545A KR102845796B1 KR 102845796 B1 KR102845796 B1 KR 102845796B1 KR 1020210142545 A KR1020210142545 A KR 1020210142545A KR 20210142545 A KR20210142545 A KR 20210142545A KR 102845796 B1 KR102845796 B1 KR 102845796B1
Authority
KR
South Korea
Prior art keywords
transistor
drain
terminal
source
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020210142545A
Other languages
English (en)
Korean (ko)
Other versions
KR20220067490A (ko
Inventor
시게유키 오카베
Original Assignee
에이블릭 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에이블릭 가부시키가이샤 filed Critical 에이블릭 가부시키가이샤
Publication of KR20220067490A publication Critical patent/KR20220067490A/ko
Application granted granted Critical
Publication of KR102845796B1 publication Critical patent/KR102845796B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
KR1020210142545A 2020-11-17 2021-10-25 지연 회로 Active KR102845796B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路
JPJP-P-2020-190639 2020-11-17

Publications (2)

Publication Number Publication Date
KR20220067490A KR20220067490A (ko) 2022-05-24
KR102845796B1 true KR102845796B1 (ko) 2025-08-13

Family

ID=78598891

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020210142545A Active KR102845796B1 (ko) 2020-11-17 2021-10-25 지연 회로

Country Status (6)

Country Link
US (1) US11437984B2 (enExample)
EP (1) EP4002690B1 (enExample)
JP (1) JP7465200B2 (enExample)
KR (1) KR102845796B1 (enExample)
CN (1) CN114513197B (enExample)
TW (1) TWI854165B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102480273B1 (ko) * 2020-12-03 2022-12-23 주식회사 지2터치 Ｐ형 트랜지스터를 포함하는 프로그램 가능한 전압이 인가되는 터치 스크린

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124858A (ja) 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
US20090256612A1 (en) 2008-04-14 2009-10-15 Hynix Semiconductor, Inc. Delay circuit and semiconductor memory device including the same
US20090261879A1 (en) * 2006-11-07 2009-10-22 Manoj Sinha Voltage and temperature compensation delay system and method

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5179539A (en) * 1988-05-25 1993-01-12 Hitachi, Ltd., Hitachi Vlsi Engineering Corporation Large scale integrated circuit having low internal operating voltage
JPH05110396A (ja) * 1991-10-16 1993-04-30 Olympus Optical Co Ltd 信号遅延回路
JPH05304464A (ja) * 1992-04-27 1993-11-16 Nec Ic Microcomput Syst Ltd 入力バッファ回路
KR100331257B1 (ko) * 1998-06-30 2002-08-21 주식회사 하이닉스반도체 일정한지연을갖는지연회로
JP2001210093A (ja) * 2000-01-25 2001-08-03 Mitsubishi Electric Corp リペア信号発生回路
KR100399595B1 (ko) * 2000-11-23 2003-09-26 삼성전자주식회사 신호 지연회로 및 이 회로를 이용한 반도체 메모리 장치
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
KR20040014839A (ko) * 2002-08-12 2004-02-18 삼성전자주식회사 온도 변화에 따른 지연 시간의 변화를 감소시키는 지연회로
US7619457B1 (en) * 2006-01-20 2009-11-17 Marvell International Ltd. Programmable delay circuit
JP4971699B2 (ja) * 2006-06-26 2012-07-11 ルネサスエレクトロニクス株式会社 遅延回路
CN101123426A (zh) * 2006-08-10 2008-02-13 普诚科技股份有限公司 延迟电路
US7932764B2 (en) * 2007-12-06 2011-04-26 Elite Semiconductor Memory Technology Inc. Delay circuit with constant time delay independent of temperature variations
US7944262B2 (en) * 2008-05-21 2011-05-17 Elpida Memory, Inc. Duty correction circuit
JP5195547B2 (ja) 2009-03-13 2013-05-08 富士電機株式会社 半導体装置
CN101557213B (zh) * 2009-03-27 2011-12-21 华为技术有限公司 延迟单元、环形振荡器及pll电路
US20100327902A1 (en) * 2009-06-25 2010-12-30 Uniram Technology, Inc. Power saving termination circuits for dram modules
TW201317551A (zh) * 2011-10-19 2013-05-01 Ili Technology Corp 溫度感測裝置
JP2013110661A (ja) 2011-11-24 2013-06-06 Elpida Memory Inc 半導体装置
US8624652B1 (en) * 2012-07-02 2014-01-07 Sandisk Technologies Inc. Accurate low-power delay circuit
KR20140062997A (ko) * 2012-11-15 2014-05-27 삼성전기주식회사 역률 보정 장치, 이를 갖는 전원 공급 장치 및 모터 구동 장치
US9401612B2 (en) * 2014-09-16 2016-07-26 Navitas Semiconductor Inc. Pulsed level shift and inverter circuits for GaN devices
WO2016065504A1 (en) 2014-10-27 2016-05-06 Texas Instruments Incorporated Dc-dc converter with temperature, process and voltage compensated dead time delay
US10110221B1 (en) * 2018-02-21 2018-10-23 Navitas Semiconductor, Inc. Power transistor control signal gating

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002124858A (ja) 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
US20090261879A1 (en) * 2006-11-07 2009-10-22 Manoj Sinha Voltage and temperature compensation delay system and method
US20090256612A1 (en) 2008-04-14 2009-10-15 Hynix Semiconductor, Inc. Delay circuit and semiconductor memory device including the same

Also Published As

Publication number Publication date
KR20220067490A (ko) 2022-05-24
CN114513197B (zh) 2025-09-19
US20220158630A1 (en) 2022-05-19
EP4002690A1 (en) 2022-05-25
EP4002690B1 (en) 2025-10-29
CN114513197A (zh) 2022-05-17
JP7465200B2 (ja) 2024-04-10
TWI854165B (zh) 2024-09-01
US11437984B2 (en) 2022-09-06
TW202222037A (zh) 2022-06-01
JP2022079823A (ja) 2022-05-27

Similar Documents

Publication Publication Date Title
US8575987B2 (en) Level shift circuit
US7317335B2 (en) Level shifter with low leakage current
US7898321B2 (en) Driver circuit
US11677400B2 (en) Level shifter circuit and method of operating the same
US6677798B2 (en) High speed voltage level shifter
JP2019012753A (ja) 電源保護回路
JP2017079431A (ja) 電圧比較回路
JP5421075B2 (ja) 入力回路
US6753707B2 (en) Delay circuit and semiconductor device using the same
KR102845796B1 (ko) 지연 회로
US20210067156A1 (en) Gate driver circuitry
TWI641219B (zh) 電源啟動控制電路以及輸入／出控制電路
US7514960B2 (en) Level shifter circuit
US8723581B1 (en) Input buffers
US10505443B2 (en) Semiconductor device
US7642818B1 (en) High voltage tolerant input circuit capable of operating at extremely low IO supply voltage
JP2008010940A (ja) 電圧制御回路及び電圧制御回路を有する半導体集積回路
JP2020161982A (ja) 論理回路
JP4658360B2 (ja) 出力バッファ
US20100231273A1 (en) Semiconductor device
JP2017153095A (ja) 半導体回路及び半導体装置
TW201941014A (zh) 參考電壓產生電路
JP2008148024A (ja) リセット回路
WO2019058771A1 (ja) 入力回路

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

D22 Grant of ip right intended

Free format text: ST27 STATUS EVENT CODE: A-1-2-D10-D22-EXM-PE0701 (AS PROVIDED BY THE NATIONAL OFFICE)

PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-2-2-U10-U11-OTH-PR1002 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

Q13 Ip right document published

Free format text: ST27 STATUS EVENT CODE: A-4-4-Q10-Q13-NAP-PG1601 (AS PROVIDED BY THE NATIONAL OFFICE)