CN114513197B - 延迟电路 - Google Patents

延迟电路

Info

Publication number
CN114513197B
CN114513197B CN202111261435.8A CN202111261435A CN114513197B CN 114513197 B CN114513197 B CN 114513197B CN 202111261435 A CN202111261435 A CN 202111261435A CN 114513197 B CN114513197 B CN 114513197B
Authority
CN
China
Prior art keywords
transistor
drain
delay circuit
power supply
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202111261435.8A
Other languages
English (en)
Chinese (zh)
Other versions
CN114513197A (zh
Inventor
冈部茂行
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ablic Inc
Original Assignee
Ablic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ablic Inc filed Critical Ablic Inc
Publication of CN114513197A publication Critical patent/CN114513197A/zh
Application granted granted Critical
Publication of CN114513197B publication Critical patent/CN114513197B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H03K5/134—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices with field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
CN202111261435.8A 2020-11-17 2021-10-28 延迟电路 Active CN114513197B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2020-190639 2020-11-17
JP2020190639A JP7465200B2 (ja) 2020-11-17 2020-11-17 遅延回路

Publications (2)

Publication Number Publication Date
CN114513197A CN114513197A (zh) 2022-05-17
CN114513197B true CN114513197B (zh) 2025-09-19

Family

ID=78598891

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111261435.8A Active CN114513197B (zh) 2020-11-17 2021-10-28 延迟电路

Country Status (6)

Country Link
US (1) US11437984B2 (enExample)
EP (1) EP4002690B1 (enExample)
JP (1) JP7465200B2 (enExample)
KR (1) KR102845796B1 (enExample)
CN (1) CN114513197B (enExample)
TW (1) TWI854165B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102480273B1 (ko) * 2020-12-03 2022-12-23 주식회사 지2터치 Ｐ형 트랜지스터를 포함하는 프로그램 가능한 전압이 인가되는 터치 스크린

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101557213A (zh) * 2009-03-27 2009-10-14 华为技术有限公司 延迟单元、环形振荡器及pll电路
CN107112890A (zh) * 2014-10-27 2017-08-29 德克萨斯仪器股份有限公司 具有温度、工艺和电压补偿的死区时间延迟的dc‑dc转换器

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US5179539A (en) * 1988-05-25 1993-01-12 Hitachi, Ltd., Hitachi Vlsi Engineering Corporation Large scale integrated circuit having low internal operating voltage
JPH05110396A (ja) * 1991-10-16 1993-04-30 Olympus Optical Co Ltd 信号遅延回路
JPH05304464A (ja) * 1992-04-27 1993-11-16 Nec Ic Microcomput Syst Ltd 入力バッファ回路
KR100331257B1 (ko) * 1998-06-30 2002-08-21 주식회사 하이닉스반도체 일정한지연을갖는지연회로
JP2001210093A (ja) * 2000-01-25 2001-08-03 Mitsubishi Electric Corp リペア信号発生回路
JP2002124858A (ja) * 2000-08-10 2002-04-26 Nec Corp 遅延回路および方法
KR100399595B1 (ko) * 2000-11-23 2003-09-26 삼성전자주식회사 신호 지연회로 및 이 회로를 이용한 반도체 메모리 장치
JP3866594B2 (ja) * 2002-03-15 2007-01-10 Ｎｅｃエレクトロニクス株式会社 遅延回路と半導体記憶装置及び半導体記憶装置の制御方法
KR20040014839A (ko) * 2002-08-12 2004-02-18 삼성전자주식회사 온도 변화에 따른 지연 시간의 변화를 감소시키는 지연회로
US7619457B1 (en) * 2006-01-20 2009-11-17 Marvell International Ltd. Programmable delay circuit
JP4971699B2 (ja) * 2006-06-26 2012-07-11 ルネサスエレクトロニクス株式会社 遅延回路
CN101123426A (zh) * 2006-08-10 2008-02-13 普诚科技股份有限公司 延迟电路
US7557631B2 (en) * 2006-11-07 2009-07-07 Micron Technology, Inc. Voltage and temperature compensation delay system and method
US7932764B2 (en) * 2007-12-06 2011-04-26 Elite Semiconductor Memory Technology Inc. Delay circuit with constant time delay independent of temperature variations
KR100948076B1 (ko) 2008-04-14 2010-03-16 주식회사 하이닉스반도체 지연회로 및 이를 포함하는 반도체 메모리장치
US7944262B2 (en) * 2008-05-21 2011-05-17 Elpida Memory, Inc. Duty correction circuit
JP5195547B2 (ja) 2009-03-13 2013-05-08 富士電機株式会社 半導体装置
US20100327902A1 (en) * 2009-06-25 2010-12-30 Uniram Technology, Inc. Power saving termination circuits for dram modules
TW201317551A (zh) * 2011-10-19 2013-05-01 Ili Technology Corp 溫度感測裝置
JP2013110661A (ja) 2011-11-24 2013-06-06 Elpida Memory Inc 半導体装置
US8624652B1 (en) * 2012-07-02 2014-01-07 Sandisk Technologies Inc. Accurate low-power delay circuit
KR20140062997A (ko) * 2012-11-15 2014-05-27 삼성전기주식회사 역률 보정 장치, 이를 갖는 전원 공급 장치 및 모터 구동 장치
US9401612B2 (en) * 2014-09-16 2016-07-26 Navitas Semiconductor Inc. Pulsed level shift and inverter circuits for GaN devices
US10110221B1 (en) * 2018-02-21 2018-10-23 Navitas Semiconductor, Inc. Power transistor control signal gating

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101557213A (zh) * 2009-03-27 2009-10-14 华为技术有限公司 延迟单元、环形振荡器及pll电路
CN107112890A (zh) * 2014-10-27 2017-08-29 德克萨斯仪器股份有限公司 具有温度、工艺和电压补偿的死区时间延迟的dc‑dc转换器

Also Published As

Publication number Publication date
KR20220067490A (ko) 2022-05-24
US20220158630A1 (en) 2022-05-19
EP4002690A1 (en) 2022-05-25
EP4002690B1 (en) 2025-10-29
CN114513197A (zh) 2022-05-17
JP7465200B2 (ja) 2024-04-10
TWI854165B (zh) 2024-09-01
US11437984B2 (en) 2022-09-06
TW202222037A (zh) 2022-06-01
KR102845796B1 (ko) 2025-08-13
JP2022079823A (ja) 2022-05-27

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Address after: Udaida 4106-73, Daizi, Udaida cho, Kitakyuku, Nagano Prefecture, Japan (postcode: 389-0293)

Applicant after: ABLIC Inc.

Address before: 9-6, 3-dingmu, Mita, Tokyo, Japan

Applicant before: ABLIC Inc.

GR01 Patent grant
GR01 Patent grant