JP7330154B2 - 半導体装置及び半導体回路 - Google Patents
半導体装置及び半導体回路 Download PDFInfo
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Description
第1の実施形態の半導体装置は、第1の面と、第1の面と対向する第2の面を有する半導体層であって、第1の面の側に設けられた第1のトレンチと、第1の面の側に設けられた第2のトレンチと、第1の面の側に設けられた第3のトレンチと、を含む半導体層と、第1のトレンチの中に設けられた第1のゲート電極と、第2のトレンチの中に設けられた第2のゲート電極と、第3のトレンチの中に設けられた第3のゲート電極と、第2の面の側に設けられた第4のゲート電極と、第2の面の側に設けられた第5のゲート電極と、第1の面に接する第1の電極と、第2の面に接する第2の電極と、第1のゲート電極に電気的に接続された第1の電極パッドと、第2のゲート電極に電気的に接続された第2の電極パッドと、第3のゲート電極に電気的に接続された第3の電極パッドと、第4のゲート電極に電気的に接続された第4の電極パッドと、第5のゲート電極に電気的に接続された第5の電極パッドと、を備える。
第2の実施形態の半導体装置及び半導体回路は、第1のゲート電極は、第1の面に平行な第1の方向に延び、第4のゲート電極は、第1の面に平行で、第1の方向に直交する第2の方向に延びる点、及び、第5のゲート電極は、第4のゲート電極と直交する方向に延びる点で、第1の実施形態の半導体装置及び半導体回路と異なっている。以下、第1の実施形態と重複する内容については一部記述を省略する場合がある。
第3の実施形態の半導体装置及び半導体回路は、第3の半導体領域と第2のトレンチは離間する点で、第1の実施形態の半導体装置及び半導体回路と異なっている。以下、第1の実施形態と重複する内容については一部記述を省略する場合がある。
10a セル部
10b 終端部
12 エミッタ電極(第1の電極)
14 コレクタ電極(第2の電極)
31 メインゲート電極(第1のゲート電極)
32 コントロールゲート電極(第2のゲート電極)
33 プリゲート電極(第3のゲート電極)
34 裏面セルゲート電極(第4のゲート電極)
35 裏面終端ゲート電極(第5のゲート電極)
51 メインゲートトレンチ(第1のトレンチ)
52 コントロールゲートトレンチ(第2のトレンチ)
53 プリゲートトレンチ(第3のトレンチ)
60 セルドレイン領域(第6の半導体領域)
62 終端ドレイン領域(第7の半導体領域)
64 セルコレクタ領域(第4の半導体領域)
65 終端コレクタ領域(第5の半導体領域)
68 ドリフト領域(第1の半導体領域)
70 ベース領域(第2の半導体領域)
72 エミッタ領域(第3の半導体領域)
100 IGBT(半導体装置)
101 第1の表面ゲート電極パッド(第1の電極パッド)
102 第2の表面ゲート電極パッド(第2の電極パッド)
103 第3の表面ゲート電極パッド(第3の電極パッド)
104 第1の裏面ゲート電極パッド(第4の電極パッド)
105 第2の裏面ゲート電極パッド(第5の電極パッド)
150 制御回路
200 IGBT(半導体装置)
300 IGBT(半導体装置)
1000 半導体モジュール(半導体回路)
P1 第1の面
P2 第2の面
Claims (9)
- 第1の面と、前記第1の面と対向する第2の面を有する半導体層であって、
前記第1の面の側に設けられた第1のトレンチと、
前記第1の面の側に設けられた第2のトレンチと、
前記第1の面の側に設けられた第3のトレンチと、
を含む半導体層と、
前記第1のトレンチの中に設けられた第1のゲート電極と、
前記第2のトレンチの中に設けられた第2のゲート電極と、
前記第3のトレンチの中に設けられた第3のゲート電極と、
前記第2の面の側に設けられた第4のゲート電極と、
前記第2の面の側に設けられた第5のゲート電極と、
前記第1の面に接する第1の電極と、
前記第2の面に接する第2の電極と、
前記第1のゲート電極に電気的に接続された第1の電極パッドと、
前記第2のゲート電極に電気的に接続された第2の電極パッドと、
前記第3のゲート電極に電気的に接続された第3の電極パッドと、
前記第4のゲート電極に電気的に接続された第4の電極パッドと、
前記第5のゲート電極に電気的に接続された第5の電極パッドと、
を備える半導体装置。 - 前記半導体層は、
第1導電形の第1の半導体領域と、
前記第1の半導体領域と前記第1の面との間に設けられ、前記第1のゲート電極と対向し、前記第2のゲート電極と対向し、前記第3のゲート電極と対向する第2導電形の第2の半導体領域と、
前記第2の半導体領域と前記第1の面との間に設けられ、前記第1の電極と接する第1導電形の第3の半導体領域と、
前記第1の半導体領域と前記第2の面との間に設けられ、前記第4のゲート電極と対向し、前記第2の電極と接する第2導電形の第4の半導体領域と、
前記第1の半導体領域と前記第2の面との間に設けられ、前記第5のゲート電極と対向し、前記第2の電極と接する第2導電形の第5の半導体領域と、
前記第4の半導体領域と前記第2の面との間に設けられ、前記第2の電極と接する第1導電形の第6の半導体領域と、
前記第5の半導体領域と前記第2の面との間に設けられ、前記第2の電極と接する第1導電形の第7の半導体領域と、を含む請求項1記載の半導体装置。 - 前記半導体層は、セル部と前記セル部を囲む終端部とを有し、
前記第1のトレンチ、前記第2のトレンチ、及び前記第3のトレンチは、前記セル部の前記第1の面の側に設けられ、
前記第4のゲート電極は、前記セル部の前記第2の面の側に設けられ、
前記第5のゲート電極は、前記終端部の前記第2の面の側に設けられる請求項1又は請求項2記載の半導体装置。 - 前記第1のゲート電極は、前記第1の面に平行な第1の方向に延び、
前記第4のゲート電極は、前記第1の面に平行で、前記第1の方向に直交する第2の方向に延びる請求項1ないし請求項3いずれか一項記載の半導体装置。 - 前記第5のゲート電極は、前記第4のゲート電極と直交する方向に延びる請求項1ないし請求項4いずれか一項記載の半導体装置。
- 前記第1の電極パッド、前記第2の電極パッド、及び前記第3の電極パッドは、前記半導体層の前記第1の面の側に設けられ、
前記第4の電極パッド及び前記第5の電極パッドは、前記半導体層の前記第2の面の側に設けられる請求項1ないし請求項5いずれか一項記載の半導体装置。 - 請求項1ないし請求項6いずれか一項記載の半導体装置と、
前記第1の電極パッド、前記第2の電極パッド、前記第3の電極パッド、前記第4の電極パッド、及び前記第5の電極パッドに印加する電圧を制御する制御回路を、備える半導体回路。 - 前記制御回路は、
前記第1の電極パッド、前記第2の電極パッド、及び前記第3の電極パッドに、前記半導体層の前記第1のゲート電極と対向する部分、前記第2のゲート電極と対向する部分、及び前記第3のゲート電極と対向する部分に反転層が形成される閾値電圧以上のターンオン電圧を印加した後、所定の時間経過後に前記第3の電極パッドに前記閾値電圧未満のターンオフ電圧を印加し、
前記第3の電極パッドにターンオフ電圧を印加した後、所定の時間経過後に前記第5の電極パッドにターンオン電圧を印加し、
前記第5の電極パッドにターンオン電圧を印加した後、所定の時間経過後に前記第4の電極パッドにターンオン電圧を印加する請求項7記載の半導体回路。 - 前記制御回路は、
前記第1の電極パッド、前記第2の電極パッド、及び前記第3の電極パッドにターンオン電圧を印加した後、所定の時間経過後に前記第1の電極パッドにターンオフ電圧を印加し、
前記第1の電極パッドにターンオフ電圧を印加する前に、前記第5の電極パッドにターンオン電圧を印加する請求項8記載の半導体回路。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2020155895A JP7330154B2 (ja) | 2020-09-16 | 2020-09-16 | 半導体装置及び半導体回路 |
CN202110827985.5A CN114267731A (zh) | 2020-09-16 | 2021-07-22 | 半导体装置以及半导体电路 |
US17/471,079 US11984495B2 (en) | 2020-09-16 | 2021-09-09 | Semiconductor device and semiconductor circuit |
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