JP7325552B2 - 高記憶密度化3次元フラッシュメモリデバイス - Google Patents
高記憶密度化3次元フラッシュメモリデバイス Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 35
- 239000004065 semiconductor Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 3
- 230000001788 irregular Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
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- 238000003491 array Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
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- 230000003247 decreasing effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
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- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
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- H10B—ELECTRONIC MEMORY DEVICES
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Description
10 基板
111 垂直NORストリング
112 グローバルソース線 (GSL)、信号ライン
113 ワード線(WL)
114 グローバルビット線(GBL)、信号ライン
200 基板
206 柱身バイアスソース
211 ビットラインアクセス選択トランジスタ
223 ワード線
256 コンタクト
257 コンタクト
270 垂直NORストリングのTFT
310 絶縁分離
314-0~314-7 グローバルビット線(GBL)
320、320a、320b チャネルブレーカ
323p ワード線スタック
334 電荷蓄積素子
354a~354d ローカルビット線(LBL)
355、355a~355d ローカルソース線(LSL)
356 チャネル領域、環状シリコンチャネル
356a、356b、356-1~356-8 チャネル領域
Claims (16)
- 基板と、
前記基板上方に配置された、垂直方向に沿って延在する半導体材料の円柱と、
前記円柱の周りを覆っているワード線スタックと、
前記ワード線スタックと前記円柱との間に配置された電荷蓄積要素と、を含み、前記円柱、前記電荷蓄積要素、および前記ワード線スタックは、少なくとも2つのメモリセルを構成する、3次元フラッシュメモリデバイスであって、
前記少なくとも2つのメモリセルのうちの2つは、前記垂直方向に沿って延在する共通のローカルソース線を含み、
前記少なくとも2つのメモリセルのうちの2つは、前記垂直方向に沿って延在し、前記少なくとも2つのメモリセルのうちの2つを分離する、チャネルブレーカを含み、
前記円柱は、前記垂直方向に沿って延在する、少なくとも2つのローカルビット線および前記共通のローカルソース線を備え、
前記3次元フラッシュメモリデバイスは、
前記少なくとも2つのローカルビット線のうちの第1のローカルビット線と、前記共通のローカルソース線との間の第1のチャネル領域と、
前記少なくとも2つのローカルビット線のうちの第2のローカルビット線と、前記共通のローカルソース線との間の第2のチャネル領域と、を含み、
前記チャネルブレーカは、前記第1のチャネル領域を前記第2のチャネル領域から分離する、
3次元フラッシュメモリデバイス。 - 前記チャネルブレーカは、絶縁層を含む、請求項1に記載の3次元フラッシュメモリデバイス。
- 前記チャネルブレーカは、前記少なくとも2つのローカルビット線を分離することによって前記少なくとも2つのメモリセルを分離する、請求項1に記載の3次元フラッシュメモリデバイス。
- ワード線を含む前記ワード線スタックが、前記垂直方向と直角をなす第2の方向に沿って延在する、請求項3に記載の3次元フラッシュメモリデバイス。
- 前記少なくとも2つのメモリセルのうちの2つは、前記ワード線および前記少なくとも2つのローカルビット線によって制御されるように構成される、請求項4に記載の3次元フラッシュメモリデバイス。
- 前記少なくとも2つのローカルビット線が、2つのグローバルビット線にそれぞれ電気的に結合されている、請求項4に記載の3次元フラッシュメモリデバイス。
- 前記2つのグローバルビット線が、前記第2の方向および前記垂直方向と直角をなす第3の方向に沿って延在する、請求項6に記載の3次元フラッシュメモリデバイス。
- 前記2つのグローバルビット線が、選択トランジスタに電気的に結合されており、前記選択トランジスタが、前記2つのグローバルビット線を前記少なくとも2つのローカルビット線に接続する、請求項6に記載の3次元フラッシュメモリデバイス。
- 基板と、
前記基板上方に配置された半導体材料の複数の円柱であって、前記複数の円柱の各々が、垂直方向に沿って延在する、複数の円柱と、
前記複数の円柱の周りを覆っているワード線スタックと、
前記ワード線スタックと前記複数の円柱の各々との間に配置された電荷蓄積要素と、を含み、前記複数の円柱の各々、前記電荷蓄積要素、および前記ワード線スタックは、複数のメモリセルを構成し、
前記複数のメモリセルは、前記垂直方向に沿って延在する少なくとも1つの共通のローカルソース線を含み、
前記複数の円柱の各々は、前記垂直方向に沿って延在する、複数のローカルビット線および複数のローカルソース線を備え、複数のチャネル領域が、前記複数のローカルビット線と複数のローカルソース線との間に配置されており、
前記複数のチャネル領域のうちの2つの間を分離するチャネルブレーカをさらに備える、
3次元フラッシュメモリデバイス。 - 前記複数のメモリセルのうちの各々2つは、前記垂直方向に沿って延在する、少なくとも2つのローカルビット線および前記少なくとも1つの共通のローカルソース線を備える、請求項9に記載の3次元フラッシュメモリデバイス。
- ワード線を含む前記ワード線スタックが、前記垂直方向と直角をなす第2の方向に沿って延在する、請求項10に記載の3次元フラッシュメモリデバイス。
- 前記複数のメモリセルのうちの各々2つは、ワード線および前記少なくとも2つのローカルビット線によって制御されるように構成される、請求項11に記載の3次元フラッシュメモリデバイス。
- 前記複数のローカルビット線が、複数のグローバルビット線にそれぞれ電気的に結合されている、請求項11に記載の3次元フラッシュメモリデバイス。
- 前記複数のグローバルビット線が、前記第2の方向および前記垂直方向と直角をなす第3の方向に沿って延在する、請求項13に記載の3次元フラッシュメモリデバイス。
- 前記複数のグローバルビット線の各々が、選択トランジスタに電気的に結合されており、前記選択トランジスタが、前記複数のグローバルビット線を前記複数のローカルビット線に接続する、請求項13に記載の3次元フラッシュメモリデバイス。
- 前記チャネルブレーカが、前記複数のローカルビット線のうちの2つの間に配置される、請求項9に記載の3次元フラッシュメモリデバイス。
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CN109801922B (zh) * | 2019-01-31 | 2020-10-20 | 长江存储科技有限责任公司 | 一种形成三维存储器的方法及三维存储器 |
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TWI725648B (zh) | 2021-04-21 |
EP3963628A1 (en) | 2022-03-09 |
JP2022538095A (ja) | 2022-08-31 |
TW202101679A (zh) | 2021-01-01 |
US11211400B2 (en) | 2021-12-28 |
KR102672972B1 (ko) | 2024-06-05 |
CN111613623A (zh) | 2020-09-01 |
US20200411539A1 (en) | 2020-12-31 |
WO2020258246A1 (en) | 2020-12-30 |
CN110520990A (zh) | 2019-11-29 |
KR20220010027A (ko) | 2022-01-25 |
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CN111613623B (zh) | 2021-02-19 |
US11956962B2 (en) | 2024-04-09 |
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