JP7280278B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP7280278B2 JP7280278B2 JP2020546018A JP2020546018A JP7280278B2 JP 7280278 B2 JP7280278 B2 JP 7280278B2 JP 2020546018 A JP2020546018 A JP 2020546018A JP 2020546018 A JP2020546018 A JP 2020546018A JP 7280278 B2 JP7280278 B2 JP 7280278B2
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- electrode
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Description
図1~図16に基づき、第1実施形態にかかる半導体装置A10について説明する。
次に、図17および図18に基づき、半導体装置A10の第1変形例である半導体装置A11について説明する。半導体装置A11は、複数の第1検出導電体52Aおよび複数の第2検出導電体52Bの各々の枕部521と、複数の第1ゲート導電体53Aおよび複数の第2ゲート導電体53Bの各々の枕部531との構成が、先述した半導体装置A10における構成と異なる。
次に、図19~図22に基づき、半導体装置A10の第2変形例である半導体装置A12について説明する。半導体装置A12は、複数の第1検出導電体52Aおよび複数の第2検出導電体52Bの構成が、先述した半導体装置A10における構成と異なる。
次に、図23~図26に基づき、半導体装置A10の第3変形例である半導体装置A13について説明する。半導体装置A13は、複数の第1検出導電体52A、複数の第2検出導電体52B、複数の第1ゲート導電体53Aおよび複数の第2ゲート導電体53Bの構成が、先述した半導体装置A10における構成と異なる。これらのうち、複数の第1検出導電体52Aおよび複数の第2検出導電体52B構成は、先述した半導体装置A12における構成と同様であるため、その説明は省略する。
図27~図32に基づき、第2実施形態にかかる半導体装置A20について説明する。これらの図において、先述した半導体装置A10の同一または類似の要素には同一の符号を付して、重複する説明を省略する。ここで、図27は、理解の便宜上、封止樹脂60を透過している。透過した封止樹脂60を想像線(二点鎖線)で示している。
次に、図33および図34に基づき、半導体装置A20の第1変形例である半導体装置A21について説明する。半導体装置A21は、複数の第1検出導電体52Aおよび複数の第2検出導電体52Bの構成が、先述した半導体装置A20における構成と異なる。
次に、図35および図36に基づき、半導体装置A20の第2変形例である半導体装置A22について説明する。半導体装置A22は、複数の第1検出導電体52A、複数の第2検出導電体52B、複数の第1ゲート導電体53Aおよび複数の第2ゲート導電体53Bの構成が、先述した半導体装置A20における構成と異なる。これらのうち、複数の第1検出導電体52Aおよび複数の第2検出導電体52B構成は、先述した半導体装置A21における構成と同様であるため、その説明は省略する。
Claims (16)
- 厚さ方向の一方側を向く主面を有する絶縁支持部材と、
前記主面に配置された第1導電層および第2導電層と、
前記主面に対向する第1サイド、および、前記厚さ方向において前記第1サイドとは反対側の第2サイドを有する第1半導体素子であって、前記第2サイドに設けられた第1電極および第2電極、ならびに前記第1サイドに設けられた第3電極を備え、前記第3電極が前記第1導電層に電気的に接合されている第1半導体素子と、
前記第1電極と前記第2導電層との各々に接続された銅または銅合金の金属片からなる第1リードと、
前記第1電極に接続された第1検出導電体と、
前記第2電極に接続された第1ゲート導電体と、を備え、
前記第1検出導電体および前記第1ゲート導電体の各々は、前記第1半導体素子に接続された第1枕部と、前記第1枕部に接続された第1ワイヤ部と、を有し、
前記第1枕部の線膨張係数は、前記第1導電層の線膨張係数よりも小である、半導体装置。 - 前記第1半導体素子と前記第1枕部とを接続する接合層をさらに備え、
前記接合層は、焼成銀から構成される、請求項1に記載の半導体装置。 - 前記第1枕部は、鉄およびニッケルを含む合金から構成される第1層と、前記第1層とは異なる金属から構成される一対の第2層と、を有し、
前記第1層は、前記厚さ方向において前記一対の第2層に挟まれている、請求項1または2に記載の半導体装置。 - 前記第1枕部は、半導体材料から構成される第1層と、金属から構成される一対の第2層と、を有し、
前記第1層は、前記厚さ方向において前記一対の第2層に挟まれている、請求項1または2に記載の半導体装置。 - 厚さ方向の一方側を向く主面を有する絶縁支持部材と、
前記主面に配置された第1導電層および第2導電層と、
前記主面に対向する第1サイド、および、前記厚さ方向において前記第1サイドとは反対側の第2サイドを有する第1半導体素子であって、前記第2サイドに設けられた第1電極および第2電極、ならびに前記第1サイドに設けられた第3電極を備え、前記第3電極が前記第1導電層に電気的に接合されている第1半導体素子と、
前記第1電極と前記第2導電層との各々に接続された銅または銅合金の金属片からなる第1リードと、
前記第1電極に接続された第1検出導電体と、
前記第2電極に接続された第1ゲート導電体と、を備え、
前記第1検出導電体は、金属片から構成され、
前記第1ゲート導電体は、前記第1半導体素子に接続された第1枕部と、前記第1枕部に接続された第1ワイヤ部と、を有し、
前記第1検出導電体および前記第1枕部の各々の線膨張係数が、前記第1導電層の線膨張係数よりも小である、半導体装置。 - 前記第1検出導電体は、鉄およびニッケルを含む合金から構成される第1層と、前記第1層とは異なる金属から構成される一対の第2層と、を有し、
前記第1層は、前記厚さ方向において前記一対の第2層に挟まれている、請求項5に記載の半導体装置。 - 厚さ方向の一方側を向く主面を有する絶縁支持部材と、
前記主面に配置された第1導電層および第2導電層と、
前記主面に対向する第1サイド、および、前記厚さ方向において前記第1サイドとは反対側の第2サイドを有する第1半導体素子であって、前記第2サイドに設けられた第1電極および第2電極、ならびに前記第1サイドに設けられた第3電極を備え、前記第3電極が前記第1導電層に電気的に接合されている第1半導体素子と、
前記第1電極と前記第2導電層との各々に接続された銅または銅合金の金属片からなる第1リードと、
前記第1電極に接続された第1検出導電体と、
前記第2電極に接続された第1ゲート導電体と、を備え、
前記第1検出導電体および前記第1ゲート導電体の各々は、金属片から構成され、
前記第1検出導電体および前記第1ゲート導電体の各々の線膨張係数が、前記第1導電層の線膨張係数よりも小である、半導体装置。 - 前記第1検出導電体が接続された第1検出配線層と、前記第1ゲート導電体が接続された第1ゲート配線層と、をさらに備え、
前記厚さ方向に視て、前記第1検出配線層および前記第1ゲート配線層は、前記主面に重なっている、請求項1ないし7のいずれかに記載の半導体装置。 - 前記第1検出配線層および前記第1ゲート配線層は、前記主面に配置されている、請求項8に記載の半導体装置。
- 前記第1導電層の上に配置された絶縁層をさらに備え、
前記第1検出配線層および前記第1ゲート配線層は、前記絶縁層の上に配置されている、請求項8に記載の半導体装置。 - 前記第1電極、前記第2電極および前記第3電極にそれぞれ対応する第4電極、第5電極および第6電極を有する第2半導体素子であって、前記第6電極が前記第2導電層に電気的に接合された第2半導体素子と、
前記第4電極に接続された銅または銅合金の金属片からなる第2リードと、
前記第4電極に接続された第2検出導電体と、
前記第5電極に接続された第2ゲート導電体と、
をさらに備える構成において、
前記第1検出導電体および前記第1ゲート導電体の各々は、前記第2半導体素子に接続された第2枕部と、前記第2枕部に接続された第2ワイヤ部と、を有し、
前記第2枕部の線膨張係数は、前記第2導電層の線膨張係数よりも小である、請求項1に記載の半導体装置。 - 厚さ方向の一方側を向く主面を有する絶縁支持部材と、
前記主面に配置された第1導電層および第2導電層と、
前記主面に対向する第1サイド、および、前記厚さ方向において前記第1サイドとは反対側の第2サイドを有する第1半導体素子であって、前記第2サイドに設けられた第1電極および第2電極、ならびに前記第1サイドに設けられた第3電極を備え、前記第3電極が前記第1導電層に電気的に接合されている第1半導体素子と、
前記第1電極と前記第2導電層との各々に接続された銅または銅合金の金属片からなる第1リードと、
前記第1電極に接続された第1検出導電体と、
前記第2電極に接続された第1ゲート導電体と、
前記第1電極、前記第2電極および前記第3電極にそれぞれ対応する第4電極、第5電極および第6電極を有する第2半導体素子であって、前記第6電極が前記第2導電層に電気的に接合された第2半導体素子と、
前記第4電極に接続された銅または銅合金の金属片からなる第2リードと、
前記第4電極に接続された第2検出導電体と、
前記第5電極に接続された第2ゲート導電体と、を備え、
前記第1検出導電体および前記第2検出導電体の各々は、金属片から構成され、
前記第1ゲート導電体は、前記第1半導体素子に接続された第1枕部と、前記第1枕部に接続された第1ワイヤ部と、を有し、
前記第2ゲート導電体は、前記第2半導体素子に接続された第2枕部と、前記第2枕部に接続された第2ワイヤ部と、を有し、
前記第1検出導電体および前記第1枕部の各々の線膨張係数が、前記第1導電層の線膨張係数よりも小であり、
前記第2検出導電体および前記第2枕部の各々の線膨張係数が、前記第2導電層の線膨張係数よりも小である、半導体装置。 - 厚さ方向の一方側を向く主面を有する絶縁支持部材と、
前記主面に配置された第1導電層および第2導電層と、
前記主面に対向する第1サイド、および、前記厚さ方向において前記第1サイドとは反対側の第2サイドを有する第1半導体素子であって、前記第2サイドに設けられた第1電極および第2電極、ならびに前記第1サイドに設けられた第3電極を備え、前記第3電極が前記第1導電層に電気的に接合されている第1半導体素子と、
前記第1電極と前記第2導電層との各々に接続された銅または銅合金の金属片からなる第1リードと、
前記第1電極に接続された第1検出導電体と、
前記第2電極に接続された第1ゲート導電体と、
前記第1電極、前記第2電極および前記第3電極にそれぞれ対応する第4電極、第5電極および第6電極を有する第2半導体素子であって、前記第6電極が前記第2導電層に電気的に接合された第2半導体素子と、
前記第4電極に接続された銅または銅合金の金属片からなる第2リードと、
前記第4電極に接続された第2検出導電体と、
前記第5電極に接続された第2ゲート導電体と、を備え、
前記第1検出導電体、前記第1ゲート導電体、前記第2検出導電体および前記第2ゲート導電体の各々は、金属片から構成され、
前記第1検出導電体および前記第1ゲート導電体の各々の線膨張係数が、前記第1導電層の線膨張係数よりも小であり、
前記第2検出導電体および前記第2ゲート導電体の各々の線膨張係数が、前記第2導電層の線膨張係数よりも小である、半導体装置。 - 前記第2検出導電体が接続された第2検出配線層と、
前記第2ゲート導電体が接続された第2ゲート配線層と、
をさらに備える構成において、
前記厚さ方向に視て、前記第2検出配線層および前記第2ゲート配線層は、前記主面に重なっている、請求項11ないし13のいずれかに記載の半導体装置。 - 前記第1導電層に導通する第1入力端子と、
前記第2リードに導通する第2入力端子と、
前記第2導電層に導通する出力端子と、
をさらに備える構成において、
前記第1入力端子および前記第2入力端子の各々は、前記厚さ方向に対して直交する一方向において、前記出力端子から離れて配置されており、
前記第2リードは、前記第2入力端子につながっている、請求項11ないし14のいずれかに記載の半導体装置。 - 前記第1入力端子および前記第2入力端子は、前記厚さ方向において互いに離れており、
前記厚さ方向に視て、前記第2入力端子の一部が、前記第1入力端子に重なっている、請求項15に記載の半導体装置。
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