JP7230679B2 - 半導体素子の製造方法 - Google Patents
半導体素子の製造方法 Download PDFInfo
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Description
最初に本願発明の実施形態の内容を列記して説明する。
(2)前記第1金属板と前記第2の金属板とは金属拡散接合により接合されてもよい。接着剤を用いないため、接着剤に起因する汚染が抑制される。
(3)前記第1金属板および前記第2金属板はステンレス鋼の板でもよい。ステンレス鋼を精度高く加工することが可能であるため、厚さのばらつきを抑制することができる。したがって小片の高さのばらつきを低減することができる。
(4)前記第1金属板の厚さのばらつきは0.010mm以下でもよい。小片の高さのばらつきを効果的に低減することができる。
(5)前記第2金属板は、前記第1金属板との接合面とは反対側の面にマークを有してもよい。マークを位置合わせに用いることで、サセプタのアライメントを精度高く行うことができる。
(6)前記第2金属板は前記第1開口部と連続する第2開口部を有してもよい。小片の配置を容易に行うことができる。
(7)前記第1金属板は前記第1開口部と重なる位置に第3開口部を有してもよい。第3開口部を介して第1開口部内を吸引することで小片をサセプタ内に吸着して、固定することができる。
(8)化合物半導体基板の上に複数の化合物半導体層を積層する工程と、前記化合物半導体層を積層する工程の後、前記化合物半導体基板を分割することで、前記化合物半導体基板から小片を形成する工程と、上記のサセプタの第1開口部に前記小片を配置する工程と、シリコンを含む第1基板に導波路メサを形成する工程と、前記サセプタと前記第1基板とを対向させ、前記小片と前記第1基板とを接合する工程と、を有する半導体素子の製造方法である。第1金属板および第2金属板を精度高く加工することができ、第1金属板の厚さのばらつきを抑制することができる。したがって小片の高さのばらつきを低減することができる。
本願発明の実施形態に係るサセプタおよび半導体素子の製造方法の具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
図1(a)は実施例1に係るサセプタ100を例示する平面図である。図1(b)はサセプタ100を例示する断面図であり、図1(a)の線A-Aに沿った断面を図示する。
図2(a)に示すように、ステンレス鋼の板から金属板60を形成する。金属板60の表面を研磨し、厚さT1を0.5±0.003mmとする。図2(b)に示すように、ステンレス鋼の板から金属板62を形成する。例えばフォトエッチング法などで金属板62に複数の開口部62aを形成する。開口部62aは金属板62を貫通する。金属板62の表面を研磨し、厚さT2を0.2±0.003mmとする。金属板60および62の表面を研磨して平坦にする。平坦な面同士を接触させ、接着剤などを用いずに金属拡散接合により接合する。これによりサセプタ100を形成する。
次にサセプタ100を用いて製造される半導体素子について説明する。図3(a)は半導体素子110を例示する斜視図であり、図3(b)は半導体素子110を例示する断面図であり、図3(a)の線B-Bに沿った断面を図示する。図3(a)および図3(b)に示すように、半導体素子110は、基板40、SiO2層42、Si層44、メサ30、絶縁膜54、p型配線56およびn型配線58を備える。
図4(a)および図5は半導体素子110の製造方法を例示する平面図である。図4(b)、図6(b)から図7(b)は半導体素子110の製造方法を例示する断面図である。図6(a)および図7(c)は半導体素子110の製造方法を例示する斜視図である。
図4(a)および図4(b)は化合物半導体のウェハ11に行われる工程を示す。ウェハ11は半導体基板10で形成されている。例えば有機金属気相成長法(MOVPE:Metal Organic Vapor Phase Epitaxy)または分子線エピタキシー法(MBE:Molecular Beam Epitaxy)などで、半導体基板10の上に、エッチングストップ層12および14、p型コンタクト層16、p型クラッド層18、活性層20、n型コンタクト層22を順にエピタキシャル成長する。
図5から図6(c)はウェハ41に行われる工程を示す。図6(b)は図6(a)の線C-Cに沿った断面図であり、図6(c)は線D-Dに沿った断面図である。図5に示すウェハ41は例えば8インチのウェハであり、図6(a)に示すようにSiの基板40、SiO2層42およびSi層44を含むSOI(シリコン・オン・インシュレータ)基板である。例えば、基板40の厚さは520μm、SiO2層42の厚さは3μm、Si層の厚さは220nmである。
図7(a)および図7(b)は接合の工程を示す断面図であり、図7(c)は接合後の状態を示す斜視図である。図7(a)に示すように、サセプタ100の複数の開口部62aの内部に小片32を配置する。小片32のサセプタ100への配置に際して、ピンセットで小片32を把持してもよいし、コレットで小片32を吸着および搬送してもよい。小片32の下面は金属板60の表面に接触し、小片32の上面は金属板62の上面から突出する。小片32の下面は図4(b)に示した半導体基板10の表面であり、上面はn型コンタクト層22の表面である。小片32の高さH1は例えば0.35mmである。小片32と金属板60との間に接着剤は設けず、また小片32の上面にも接着剤を塗布しない。
11、41 ウェハ
11a スクライブライン
12、14 エッチングストップ層
16 p型コンタクト層
18 p型クラッド層
20 活性層
22 n型コンタクト層
30 メサ
32 小片
40 基板
42 SiO2層
44 Si層
45 壁
46 導波路メサ
47 溝
48 テラス
53 p型電極
54 絶縁膜
55 n型電極
56 p型配線
58 n型配線
60、62、64,66 金属板
60a、62a、64a、66a 開口部
70、72 マーク
70a、70b、72a、72b 溝
74 吸引部
100、200、300、400 サセプタ
110 半導体素子
Claims (7)
- サセプタを用いる半導体素子の製造方法であって、
前記サセプタは、
第1金属板と、
前記第1金属板の表面に接合された第2金属板と、を具備し、
前記第2金属板は複数の第1開口部を有し、
前記複数の第1開口部から前記第1金属板の表面が露出し、
前記製造方法は、
化合物半導体基板の上に複数の化合物半導体層を積層する工程と、
前記化合物半導体層を積層する工程の後、前記化合物半導体基板を分割することで、前記化合物半導体基板から小片を形成する工程と、
前記サセプタの前記第1開口部に前記小片を配置する工程と、
シリコンを含む第1基板に導波路メサを形成する工程と、
前記サセプタと前記第1基板とを対向させ、前記小片と前記第1基板とを接合する工程と、を有する半導体素子の製造方法。 - 前記第1金属板と前記第2の金属板とは金属拡散接合により接合されている請求項1に記載の半導体素子の製造方法。
- 前記第1金属板および前記第2金属板はステンレスの板である請求項1または請求項2に記載の半導体素子の製造方法。
- 前記第1金属板の厚さのばらつきは0.010mm以下である請求項1から請求項3のいずれか一項に記載の半導体素子の製造方法。
- 前記第2金属板は、前記第1金属板との接合面とは反対側の面にマークを有する請求項1から請求項4のいずれか一項に記載の半導体素子の製造方法。
- 前記第2金属板は前記第1開口部と連続する第2開口部を有する請求項1から請求項5のいずれか一項に記載の半導体素子の製造方法。
- 前記第1金属板は前記第1開口部と重なる位置に第3開口部を有する請求項1から請求項6のいずれか一項に記載の半導体素子の製造方法。
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US16/859,128 US20200365445A1 (en) | 2019-05-15 | 2020-04-27 | Susceptor and method of manufacturing semiconductor device |
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014116331A (ja) | 2011-11-30 | 2014-06-26 | Dowa Electronics Materials Co Ltd | 結晶成長装置、結晶成長方法及びサセプタ |
JP2015164148A (ja) | 2014-02-28 | 2015-09-10 | 古河電気工業株式会社 | 集積型半導体光素子、及び集積型半導体光素子の製造方法 |
JP2016197689A (ja) | 2015-04-06 | 2016-11-24 | 三菱電機株式会社 | 半導体試験治具、半導体装置の試験方法 |
JP2018022728A (ja) | 2016-08-02 | 2018-02-08 | 東洋精密工業株式会社 | 部品一体型クランプトレイ |
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JP2014116331A (ja) | 2011-11-30 | 2014-06-26 | Dowa Electronics Materials Co Ltd | 結晶成長装置、結晶成長方法及びサセプタ |
JP2015164148A (ja) | 2014-02-28 | 2015-09-10 | 古河電気工業株式会社 | 集積型半導体光素子、及び集積型半導体光素子の製造方法 |
JP2016197689A (ja) | 2015-04-06 | 2016-11-24 | 三菱電機株式会社 | 半導体試験治具、半導体装置の試験方法 |
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