JP7159750B2 - 光半導体素子およびその製造方法 - Google Patents
光半導体素子およびその製造方法 Download PDFInfo
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- JP7159750B2 JP7159750B2 JP2018180453A JP2018180453A JP7159750B2 JP 7159750 B2 JP7159750 B2 JP 7159750B2 JP 2018180453 A JP2018180453 A JP 2018180453A JP 2018180453 A JP2018180453 A JP 2018180453A JP 7159750 B2 JP7159750 B2 JP 7159750B2
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Description
最初に本願発明の実施形態の内容を列記して説明する。
(2)前記小片は、前記導波路メサ、前記溝、前記テラス、および前記少なくとも2つの壁に重なるように前記基板に接合され、前記メサは前記少なくとも2つの壁に重ならず、前記溝の延伸方向において前記少なくとも2つの壁の間に位置してもよい。溝が小片、テラスおよび壁により閉塞されるため、エッチャントの侵入が効果的に抑制される。したがって小片の剥離が効果的に抑制される。また、メサが2つの壁の間に位置するため、エッチャントによるダメージを受けにくい。したがって光半導体素子の特性が安定する。
(3)前記導波路メサおよび前記壁は同じ高さを有してもよい。小片が導波路メサ、テラスおよび壁によって溝が閉塞される。したがってエッチャントの侵入が効果的に抑制され、小片の剥離が抑制される。
(4)前記壁は前記導波路メサに直交してもよい。壁により溝からのエッチャントの侵入が抑制され、小片の剥離が抑制される。
(5)前記壁と前記溝の延伸方向との間の角度は30°以上、60°以下でもよい。壁により溝からのエッチャントの侵入が抑制され、小片の剥離が抑制される。また、壁による光の反射が抑制されるため、反射光が共振して能動素子の動作を不安定にすることが抑制される。
(6)前記壁は前記導波路メサおよび前記テラスに接続してもよい。壁により溝が閉塞されるため、エッチャントの侵入が効果的に抑制され、小片の剥離が抑制される。
(7)前記壁は前記導波路メサおよび前記テラスの一方に接続し、他方に接続せず、複数の前記壁が前記溝の延伸方向に沿って形成され、前記溝の延伸方向において前記メサの両側のそれぞれに複数の前記壁が位置してもよい。エッチャントの表面張力により、エッチャントが壁を通過するまでに時間がかかり、壁を複数とすることでさらに長い時間がかかる。したがって小片の化合物半導体層がエッチングされる前に、化合物半導体基板のエッチングが完了する。これにより小片の剥離が抑制される。
(8)前記壁は前記導波路メサに接続し、前記テラスに接続しなくてもよい。壁が回折格子として機能する。
(9)前記溝の延伸方向における前記壁の厚さは0.1μm以上、2μm以下でもよい。これにより、化合物半導体基板のエッチングにおいて、壁により溝からのエッチャントの侵入が抑制され、化合物半導体層までエッチングが進行しにくくなる。また、光が壁を通過する際に発生する光損失を抑えることが可能となる。
(10)シリコンを含む基板と、前記基板に接合され、化合物半導体層を含む小片と、を具備し、前記基板は導波路メサ、テラス、溝および壁を有し、前記溝は前記導波路メサの両側に位置し、前記テラスは前記導波路メサおよび前記溝の両側に位置し、少なくとも2つの前記壁が前記溝の延伸方向に並び、前記壁は前記溝の延伸方向に交差し、前記小片は前記導波路メサに対向するメサを有する光半導体素子である。壁により溝からのエッチャントの侵入が抑制される。このため化合物半導体層のエッチングが抑制され、小片の剥離が抑制される。
本発明の実施形態に係る光半導体素子およびその製造方法の具体例を、以下に図面を参照しつつ説明する。なお、本発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味および範囲内でのすべての変更が含まれることが意図される。
図1(a)は実施例1に係る光半導体素子100を例示する斜視図であり、図1(b)は図1(a)の線A-Aに沿った断面図である。図1(a)および図1(b)に示すように、光半導体素子100は、基板40、SiO2層42、Si層44、メサ30、絶縁膜54、p型配線56およびn型配線58を備える。
図2(a)および図3(a)は光半導体素子の製造方法を例示する平面図である。図3(b)は壁45を拡大した平面図である。図5(a)および図8(a)は光半導体素子の製造方法を例示する斜視図であり、図2(b)、図4(b)および図4(c)、図5(b)から図7(b)、図8(b)から図9(c)は光半導体装置の製造方法を例示する断面図である。
図2(a)および図2(b)は化合物半導体で形成されたウェハ11に行われる工程を示す。ウェハ11は半導体基板10で形成されている。例えば有機金属気相成長法(MOVPE:Metal Organic Vapor Phase Epitaxy)または分子線エピタキシー法(MBE:Molecular Beam Epitaxy)などで、半導体基板10の上に、エッチングストップ層12および14、p型コンタクト層16、p型クラッド層18、活性層20、n型コンタクト層22を順にエピタキシャル成長する。
図3(a)から図4(c)はウェハ41に行われる工程を示す。図4(b)は図3(b)の線A-Aに沿った断面図であり、図4(c)は線B-Bに沿った断面図である。ウェハ41は例えば8インチのウェハであり、Siの基板40、SiO2層42およびSi層44を含むSOI(シリコン・オン・インシュレータ)基板である。例えば、基板40の厚さは520μm、SiO2層42の厚さは3μm、Si層の厚さは220nmである。
図5(a)から図9(c)は接合およびそれ以降の工程を示す。図5(a)に示すように小片32をウェハ41に接合する。ウェハ41には複数の小片32を接合し、1つの小片32は1つの導波路メサ46、2つの溝47、4つの壁45、テラス48の一部に重なる。小片32は領域R1より長いため、小片32は領域R1にも重なる。小片32のn型コンタクト層22はSi層44に接触する。
11、41 ウェハ
11a スクライブライン
12、14 エッチングストップ層
16 p型コンタクト層
18 p型クラッド層
20 活性層
22 n型コンタクト層
30 メサ
32 小片
40 基板
42 SiO2層
44 Si層
45 壁
46 導波路メサ
47 溝
48 テラス
50、52 マスク
53 p型電極
54 絶縁膜
55 n型電極
56 p型配線
58 n型配線
100 光半導体素子
Claims (9)
- 化合物半導体基板の上に複数の化合物半導体層を積層する工程と、
前記化合物半導体基板を分割することで、前記化合物半導体基板から小片を形成する工程と、
シリコンを含む基板に、導波路メサ、テラス、溝および壁を形成する工程と、
前記導波路メサ、テラス、溝および壁を形成する工程の後、前記小片を前記基板に接合する工程と、
前記接合する工程の後、前記化合物半導体層が露出するように、前記化合物半導体基板をウェットエッチングする工程と、
前記ウェットエッチングする工程の後、前記化合物半導体層から、前記導波路メサに対向するメサを形成する工程と、を有し、
前記溝は前記導波路メサの両側に形成され、
前記テラスは前記導波路メサおよび前記溝の両側に形成され、
少なくとも2つの前記壁が前記溝の延伸方向に並ぶ光半導体素子の製造方法。 - 前記小片は、前記導波路メサ、前記溝、前記テラス、および前記少なくとも2つの壁に重なるように前記基板に接合され、
前記メサは前記少なくとも2つの壁に重ならず、前記溝の延伸方向において前記少なくとも2つの壁の間に位置する請求項1に記載の光半導体素子の製造方法。 - 前記導波路メサおよび前記壁は同じ高さを有する請求項1または2に記載の光半導体素子の製造方法。
- 前記壁は前記導波路メサに直交する請求項1から3のいずれか一項に記載の光半導体素子の製造方法。
- 前記壁と前記溝の延伸方向との間の角度は30°以上、60°以下である請求項1から3のいずれか一項に記載の光半導体素子の製造方法。
- 前記壁は前記導波路メサおよび前記テラスに接続する請求項1から5のいずれか一項に記載の光半導体素子の製造方法。
- 前記壁は前記導波路メサおよび前記テラスの一方に接続し、他方に接続せず、
複数の前記壁が前記溝の延伸方向に沿って形成され、
前記溝の延伸方向において前記メサの両側のそれぞれに複数の前記壁が位置する請求項1から5のいずれか一項に記載の光半導体素子の製造方法。 - 前記壁は前記導波路メサに接続し、前記テラスに接続しない請求項7に記載の光半導体素子の製造方法。
- 前記溝の延伸方向における前記壁の厚さは0.1μm以上、2μm以下である請求項1から8のいずれか一項に記載の光半導体素子の製造方法。
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