JP7073698B2 - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Description
本発明にかかる半導体装置について、SJ-MOSFETを例に説明する。図1は、実施の形態1にかかるSJ-MOSFETの構造を示す上面図である。また、図1は、図2の酸化膜13およびp+型ベース領域5を省略した状態を上方(ソース電極10側)から見た上面図である。図2は、実施の形態1にかかるSJ-MOSFETの構造を示す図1のA-A’の断面図である。
次に、実施の形態1にかかる半導体装置の製造方法について説明する。図9~図15は、実施の形態1にかかるSJ-MOSFETの製造途中の状態を示す断面図である。まず、シリコンからなりn+型ドレイン層となるn+型半導体基板1を用意する。次に、n+型半導体基板1のおもて面上に、n+型半導体基板1より不純物濃度の低いn-型ドリフト層2をエピタキシャル成長させる。
次に、実施の形態2にかかる半導体装置の構造について説明する。図17は、実施の形態2にかかるSJ-MOSFETの構造を示す断面図である。なお、実施の形態2の活性領域200の構造は、実施の形態1と同様であるため、図17では、酸化膜13を除いた終端領域300の構造のみを示す。
次に、実施の形態2にかかる半導体装置の製造方法について説明する。図18~図23は、実施の形態2にかかるSJ-MOSFETの製造途中の状態を示す断面図である。まず、実施の形態1と同様に、シリコンからなりn+型ドレイン層となるn+型半導体基板1を用意する。次に、n+型半導体基板1のおもて面上に、n+型半導体基板1より不純物濃度の低いn-型ドリフト層2をエピタキシャル成長させる。
2 n-型ドリフト層
3 n型カラム領域
3a 下部n型カラム領域
3b 上部n型カラム領域
4 p型カラム領域
4a 下部p型カラム領域
5 p+型ベース領域
6 n+型ソース領域
7 ゲート絶縁膜
8 ゲート電極
9 層間絶縁膜
10 ソース電極
12 n+型領域
13 酸化膜
14 上部p型層リング
16a~16d マスク
17 p型インプラ領域
18 n型インプラ領域
19 並列pn領域
20 並列pn領域
20a 下部並列pn領域
20b 上部並列pn領域
21 n-型層
22 トレンチ
23 p型ベース領域
24、25 埋め込みトレンチ
40 等電位線
200 活性領域
300 終端領域
Claims (11)
- 電流が流れる活性領域と、前記活性領域の外側に配置された、前記活性領域の周囲を囲む耐圧構造が形成された終端構造部と、を有する半導体装置であって、
第1導電型の半導体基板のおもて面に設けられた、前記半導体基板より低不純物濃度の第1導電型の第1半導体層と、
前記第1半導体層の内部に設けられた、第1導電型の下部第1カラムと第2導電型の下部第2カラムとが前記おもて面に平行な面において繰り返し交互に配置された下部並列pn構造と、
前記終端構造部の前記下部並列pn構造の表面に設けられた、第1導電型の上部第1カラムと、前記下部第2カラムと電気的に接続する第2導電型の上部第2カラムとが前記おもて面に平行な面において繰り返し交互に配置された上部並列pn構造と、
前記活性領域の前記下部並列pn構造の表面に設けられた、第2導電型の第1半導体領域と、
を備え、
前記上部第2カラムの幅が、前記下部第2カラムの幅より広く、前記上部第2カラム間の間隔が、前記下部第2カラム間の間隔より広く、
前記上部第2カラムの膜厚は、前記第1半導体領域の膜厚より大きいことを特徴とする半導体装置。 - 前記上部第2カラムの膜厚は、前記第1半導体領域の膜厚の2.5倍以上6倍以下であることを特徴とする請求項1に記載の半導体装置。
- 前記上部第2カラムの幅は、前記下部第2カラムの幅の1.25倍以上3倍以下であり、前記上部第2カラム間の間隔は、前記下部第2カラム間の間隔の1.25倍以上3倍未満であることを特徴とする請求項1または2に記載の半導体装置。
- 前記上部第2カラムは、前記活性領域を取り囲むリング形状であることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。
- 前記終端構造部は、
前記上部並列pn構造および前記下部並列pn構造を囲むように設けられた第1導電型の第2半導体層と、
前記第2半導体層を囲むように設けられた前記第1半導体層よりも不純物濃度が高い第1導電型の第3半導体層と、を備えることを特徴とする請求項1~3のいずれか一つに記載の半導体装置。 - 前記第2半導体層は、前記第1半導体層よりも不純物濃度が低いことを特徴とする請求項5に記載の半導体装置。
- 前記第2半導体層は、前記第1半導体層と同じ不純物濃度であることを特徴とする請求項5に記載の半導体装置。
- 電流が流れる活性領域と、前記活性領域の外側に配置された、前記活性領域の周囲を囲む耐圧構造が形成された終端構造部と、を有する半導体装置の製造方法であって、
第1導電型の半導体基板のおもて面に、前記半導体基板より低不純物濃度の第1導電型の第1半導体層を形成する第1工程と、
前記第1半導体層の内部に、第1導電型の下部第1カラムと第2導電型の下部第2カラムとが前記おもて面に平行な面において繰り返し交互に配置された下部並列pn構造を形成する第2工程と、
前記終端構造部の前記下部並列pn構造の表面に、第1導電型の上部第1カラムと、前記下部第2カラムと電気的に接続する第2導電型の上部第2カラムとが前記おもて面に平行な面において繰り返し交互に配置された上部並列pn構造を形成する第3工程と、
前記活性領域の前記下部並列pn構造の表面に、第2導電型の第1半導体領域を形成する第4工程と、
を含み、
前記第3工程では、前記上部第2カラムの幅を、前記下部第2カラムの幅より広く、前記上部第2カラム間の間隔を、前記下部第2カラム間の間隔より広く、前記上部第2カラムの膜厚を、前記第1半導体領域の膜厚より大きく形成することを特徴とする半導体装置の製造方法。 - 前記第2工程では、前記下部並列pn構造をエピタキシャル成長とイオン注入を繰り返すことにより形成し、
前記第3工程では、前記上部並列pn構造をエピタキシャル成長とイオン注入を繰り返すことにより形成することを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記第2工程では、トレンチを形成し、前記トレンチ内に第1導電型または第2導電型の領域をエピタキシャル成長させ、表面を研磨することで、前記トレンチ内に第1導電型または第2導電型の不純物を埋め込むことにより前記下部並列pn構造を形成し、
前記第3工程では、トレンチを形成し、前記トレンチ内に第1導電型または第2導電型の領域をエピタキシャル成長させ、表面を研磨することで、前記トレンチ内に第1導電型または第2導電型の不純物を埋め込むことにより前記上部並列pn構造を形成することを特徴とする請求項8に記載の半導体装置の製造方法。 - 前記第3工程では、前記第2工程で用いたマスクより開口幅が1倍以上1.2倍以下のマスクを用いることを特徴とする請求項8~10のいずれか一つに記載の半導体装置の製造方法。
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