JP7052042B2 - 超伝導量子ビット回路のための低損失アーキテクチャ - Google Patents
超伝導量子ビット回路のための低損失アーキテクチャ Download PDFInfo
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Description
1)ジョセフソン接合は、非線形の無損失集中インダクタである。ジョセフソン接合は、量子ビットLC共振器の誘導部を提供する。無損失という用語が示唆するように、ジョセフソン接合は、損失の観点からは問題がない。また、ジョセフソン接合における(誘導)エネルギーは局所的に蓄積され、量子ビット102における接合は外部回路(量子ビット面202または読み出し面302あるいはその両方の面上の回路の他の部分)とは、ほとんど誘導的作用をしない。ジョセフソン接合またはジョセフソン接合の直列アレイは、螺旋コイル332の代わりとして使用することもできる。
2)仮想的にのみ励起され、光子が存在しないLC共振器。量子ビット間のバス共振器104がLC共振器のこのカテゴリに入る。仮想励起によって、バス共振器104は、その共振器104の共振周波数またはその高調波とは異なる周波数の光子の伝達を可能にする/促進する。バス共振器のモード(すなわち、共振周波数およびその高調波)が励起されないため、これらのバス共振器(およびその誘導部)により生じる損失は問題ではない。また、実際には、これらのバス共振器は極めて高いクオリティ・ファクタ(Qファクタ)、すなわち極めて低損失で作製される。
3)モードが(その共振周波数で、または場合によっては高調波でも)直接励起されるLC共振器に、(ある程度)光子が存在する。本明細書に記載の例示の量子回路では、読み出し共振器106がこのカテゴリに入る。読み出し共振器106は、外部(オフ・チップ)回路(常温電子回路まで)にも結合/接続する。本実験者らは読み出し共振器106によって生じる損失に関心を持ち、損失はその誘導部でより大きく、本発明の実施形態は、読み出し共振器106の誘導部を本明細書に記載の(影響を受けやすい)量子ビットから離す技術および構造を提供する。
Claims (16)
- 構造であって、
共振器の誘導素子を含む第1の表面と、
前記共振器の容量素子の第1の部分と少なくとも1つの量子ビットとを含む第2の表面と
を含み、前記共振器の前記容量素子の第2の部分が前記第1の表面上にあり、前記容量素子が相互接続構造を含む、構造。 - 前記相互接続構造がはんだバンプを含む、請求項1に記載の構造。
- 前記相互接続構造がスルー・シリコン・ビアを含む、請求項1または2に記載の構造。
- 前記第1の表面と前記第2の表面とが回路面を含み、前記回路面が基板の互いに反対の側にある、請求項1ないし3のいずれかに記載の構造。
- 前記第1の表面と前記第2の表面とが回路面を含み、前記回路面が異なる基板上にある、請求項1ないし4のいずれかに記載の構造。
- 前記第1の部分と前記第2の部分とを接続する前記相互接続構造が、前記相互接続構造と前記第1の部分と前記第2の部分との間に等電位を形成する、請求項1ないし5のいずれかに記載の構造。
- 前記少なくとも1つの量子ビットが容量型量子ビットを含む、請求項1ないし6のいずれかに記載の構造。
- 前記少なくとも1つの量子ビットが誘導型量子ビットを含む、請求項1ないし6のいずれかに記載の構造。
- 構造を形成する方法であって、
第1の表面に共振器の誘導素子を配置することと、
第2の表面に前記共振器の容量素子の第1の部分と少なくとも1つの量子ビットとを配置することと
を含み、前記共振器の前記容量素子の第2の部分が前記第1の表面上にある、方法。 - 構造であって、
共振器の誘導素子と前記共振器の容量素子の第1の部分とを含む第1の表面と、
バス共振器によって結合された少なくとも2つの量子ビットを含む第2の表面とを含み、前記第2の表面が前記共振器の前記容量素子の第2の部分を含む、構造。 - 前記第1の表面は第1の回路面を含み、前記第2の表面は、前記共振器の前記誘導素子と前記少なくとも2つの量子ビットとが異なる回路面上に位置するように、前記第1の回路面とは分離した第2の回路面を含む、請求項10に記載の構造。
- 前記共振器が読み出し共振器を含む、請求項10または11に記載の構造。
- 前記読み出し共振器は前記少なくとも2つの量子ビットのうちのそれぞれの量子ビットを読み出すように動作可能である、請求項12に記載の構造。
- 前記読み出し共振器のそれぞれが前記少なくとも2つの量子ビットのうちのそれぞれの量子ビットに結合された、請求項12または13に記載の構造。
- 構造を形成する方法であって、
第1の表面上に、共振器の誘導素子と、前記共振器の容量素子の第1の部分とを配置することと、
第2の表面上に、バス共振器によって結合された少なくとも2つの量子ビットを配置することと
を含み、前記第2の表面は前記共振器の前記容量素子の第2の部分を含む、方法。 - 超伝導量子ビット回路であって、
量子ビットにそれぞれ結合するように構成された読み出し共振器と、
前記量子ビットのうちの少なくとも2つの量子ビットを互いに結合するように構成された1つまたは複数のバス共振器と、
前記読み出し共振器の誘導素子を含む第1の表面と、
前記量子ビットを含む第2の表面と
を含み、前記第1の表面と前記第2の表面とが異なる回路面である、超伝導量子ビット回路。
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US15/827,718 US10305015B1 (en) | 2017-11-30 | 2017-11-30 | Low loss architecture for superconducting qubit circuits |
US15/827,718 | 2017-11-30 | ||
PCT/IB2017/058214 WO2019106416A1 (en) | 2017-11-30 | 2017-12-20 | Low loss architecture for superconducting qubit circuits |
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