JP7021821B2 - 金属ゲートプロセスに基づく低コストのフラッシュメモリ製造フロー - Google Patents

金属ゲートプロセスに基づく低コストのフラッシュメモリ製造フロー Download PDF

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JP7021821B2
JP7021821B2 JP2018506188A JP2018506188A JP7021821B2 JP 7021821 B2 JP7021821 B2 JP 7021821B2 JP 2018506188 A JP2018506188 A JP 2018506188A JP 2018506188 A JP2018506188 A JP 2018506188A JP 7021821 B2 JP7021821 B2 JP 7021821B2
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gate
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sensing
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drain
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JP2018526821A (ja
JP2018526821A5 (enExample
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タン ニン
ティエン ウェイドン
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テキサス インスツルメンツ インコーポレイテッド
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    • H10D30/6892—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode having at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
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JP2018506188A 2015-08-05 2016-08-05 金属ゲートプロセスに基づく低コストのフラッシュメモリ製造フロー Active JP7021821B2 (ja)

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Application Number Priority Date Filing Date Title
US14/819,401 2015-08-05
US14/819,401 US9431253B1 (en) 2015-08-05 2015-08-05 Fabrication flow based on metal gate process for making low cost flash memory
PCT/US2016/045895 WO2017024274A1 (en) 2015-08-05 2016-08-05 Low cost flash memory fabrication flow based on metal gate process

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JP2018526821A JP2018526821A (ja) 2018-09-13
JP2018526821A5 JP2018526821A5 (enExample) 2019-09-12
JP7021821B2 true JP7021821B2 (ja) 2022-02-17

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JP (1) JP7021821B2 (enExample)
CN (1) CN107924921B (enExample)
WO (1) WO2017024274A1 (enExample)

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KR102568562B1 (ko) * 2017-01-24 2023-08-18 삼성전자주식회사 반도체 장치
US10868027B2 (en) * 2018-07-13 2020-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Structure and method for preventing silicide contamination during the manufacture of micro-processors with embedded flash memory
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
CN113130516A (zh) * 2020-01-15 2021-07-16 联华电子股份有限公司 半导体影像感测元件及其制作方法
US20250351346A1 (en) * 2024-05-10 2025-11-13 Stmicroelectronics International N.V. Non-volatile memory cell with single poly floating gate and contact control gate

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164736A (ja) 1998-11-30 2000-06-16 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
JP2000164835A (ja) 1998-11-26 2000-06-16 Stmicroelectronics Srl 集積回路の製造方法
JP2008205379A (ja) 2007-02-22 2008-09-04 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
JP2009016688A (ja) 2007-07-06 2009-01-22 Sharp Corp 半導体装置の製造方法
JP2009044053A (ja) 2007-08-10 2009-02-26 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
US20090134444A1 (en) 2007-11-26 2009-05-28 Hanafi Hussein I Memory Cells, And Methods Of Forming Memory Cells
JP2012514346A (ja) 2008-12-31 2012-06-21 インテル コーポレイション 集積されたｈｉｇｈ−ｋ誘電体と金属ベースの制御ゲートを有するフラッシュセル
JP2012186438A (ja) 2011-03-03 2012-09-27 Ememory Technology Inc 不揮発性メモリ及びその製造方法
JP2013197533A (ja) 2012-03-22 2013-09-30 Toshiba Corp 記憶装置及びその製造方法
JP2015070261A (ja) 2013-09-27 2015-04-13 力旺電子股▲ふん▼有限公司 不揮発性メモリ構造

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5518942A (en) * 1995-02-22 1996-05-21 Alliance Semiconductor Corporation Method of making flash EPROM cell having improved erase characteristics by using a tilt angle implant
KR0179175B1 (ko) * 1995-10-05 1999-03-20 문정환 반도체 메모리 장치 및 제조방법
US6628544B2 (en) * 1999-09-30 2003-09-30 Infineon Technologies Ag Flash memory cell and method to achieve multiple bits per cell
JP3479010B2 (ja) * 1999-11-04 2003-12-15 Ｎｅｃエレクトロニクス株式会社 不揮発性半導体記憶装置の製造方法
JP3829088B2 (ja) * 2001-03-29 2006-10-04 株式会社東芝 半導体記憶装置
US6914820B1 (en) * 2002-05-06 2005-07-05 Multi Level Memory Technology Erasing storage nodes in a bi-directional nonvolatile memory cell
US6642111B1 (en) * 2002-07-09 2003-11-04 Powerchip Semiconductor Corp. Memory device structure and method of fabricating the same
JP4829015B2 (ja) * 2006-06-20 2011-11-30 株式会社東芝 不揮発性半導体記憶装置
KR101925159B1 (ko) * 2010-08-06 2018-12-04 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
CN101941696B (zh) * 2010-09-15 2012-07-04 复旦大学 一种适用于石墨烯基场效应管制造的纳米光刻方法
US8930866B2 (en) * 2013-03-11 2015-01-06 Taiwan Semiconductor Manufacturing Company, Ltd. Method of converting between non-volatile memory technologies and system for implementing the method

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000164835A (ja) 1998-11-26 2000-06-16 Stmicroelectronics Srl 集積回路の製造方法
JP2000164736A (ja) 1998-11-30 2000-06-16 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
JP2008205379A (ja) 2007-02-22 2008-09-04 Toshiba Corp 不揮発性半導体メモリ及びその製造方法
JP2009016688A (ja) 2007-07-06 2009-01-22 Sharp Corp 半導体装置の製造方法
JP2009044053A (ja) 2007-08-10 2009-02-26 Fujitsu Microelectronics Ltd 半導体装置及びその製造方法
US20090134444A1 (en) 2007-11-26 2009-05-28 Hanafi Hussein I Memory Cells, And Methods Of Forming Memory Cells
JP2012514346A (ja) 2008-12-31 2012-06-21 インテル コーポレイション 集積されたｈｉｇｈ−ｋ誘電体と金属ベースの制御ゲートを有するフラッシュセル
JP2012186438A (ja) 2011-03-03 2012-09-27 Ememory Technology Inc 不揮発性メモリ及びその製造方法
JP2013197533A (ja) 2012-03-22 2013-09-30 Toshiba Corp 記憶装置及びその製造方法
JP2015070261A (ja) 2013-09-27 2015-04-13 力旺電子股▲ふん▼有限公司 不揮発性メモリ構造

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