CN113130516A - 半导体影像感测元件及其制作方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title abstract description 4
- 239000010410 layer Substances 0.000 claims abstract description 306
- 239000011229 interlayer Substances 0.000 claims abstract description 102
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 81
- 229920005591 polysilicon Polymers 0.000 claims abstract description 81
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 62
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 57
- 239000002184 metal Substances 0.000 claims abstract description 57
- 230000004888 barrier function Effects 0.000 claims abstract description 9
- 238000000034 method Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 239000010941 cobalt Substances 0.000 claims description 7
- 229910017052 cobalt Inorganic materials 0.000 claims description 7
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 7
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- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 6
- 230000000903 blocking effect Effects 0.000 claims description 6
- 229910021334 nickel silicide Inorganic materials 0.000 claims description 6
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052715 tantalum Inorganic materials 0.000 claims description 6
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 6
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
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- 238000012986 modification Methods 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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Abstract
本发明公开一种半导体影像感测元件及其制作方法,该影像感测元件包含晶体管,设置于像素区内;硅化物挡层,覆盖像素区;第一层间介电层,覆盖硅化物挡层;第二层间介电层,位于第一层间介电层上;源极接触穿过第二、第一层间介电层和硅化物挡层,且包括在第一层间介电层中的第一多晶硅插塞,在第一多晶硅插塞上的第一自对准硅化物层,及在第一自对准硅化物层上的第一导电金属层;以及漏极接触,穿过第二、第一层间介电层和硅化物挡层,且包括在第一层间介电层中的第二多晶硅插塞,在第二多晶硅插塞上的第二自对准硅化物层,以及在第二自对准硅化物层上的第二导电金属层。
Description
技术领域
本发明涉及半导体技术领域,特别是涉及一种半导体影像感测元件(semiconductor image sensor device)及其制作方法。
背景技术
CMOS影像传感器的单位像素通常是由埋入光电二极管(buried photodiode)和四个NMOS晶体管组成。这四个NMOS晶体管包括:传输晶体管(transfer transistor),用于将在埋入光电二极管中产生的光电电荷传输到感测节点;重置晶体管(reset transistor),用于将感测节点重置以感测下一信号;驱动晶体管(drive transistor),其用作源极跟随器;以及选择晶体管(select transistor),用于响应地址讯号将数据输出到输出端子。
在CMOS影像传感器中,自对准硅化物(self-aligned silicide)可用于改善RC延迟。然而,常规的自对准硅化物制作工艺在应用于CMOS影像传感器具有一定的局限性。在CMOS影像传感器的光敏区域的大部分区域(例如光敏二极管区域和光敏区域中的源极/漏极区域)中形成硅化物通常会导致漏电流增加,从而降低传感器的图像品质。
暗电流(dark current)是目前的CMOS影像传感器技术中的最需要克服的问题。已知,暗电流可能来自硅损伤和金属污染。其中,金属污染源之一是接触洞中的钨和金属硅化物。为了降低暗电流,CMOS影像传感器通常采用非硅化金属工艺,但缺点是像素接触电阻较高,导致元件的性能较差。
发明内容
本发明的主要目的在于提供改良的半导体影像感测元件及其制作方法,以克服现有技术中的不足和缺点。
本发明一方面提供一种半导体影像感测元件,包含:一半导体基底,包含一影像感测像素区;一MOS晶体管,设置于所述半导体基底上的所述影像感测像素区内,其中所述MOS晶体管包含一源极区、一与所述源极区区隔开的漏极区、一介于所述源极区和所述漏极区的通道区,以及一位于所述通道区上的栅极;一硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;一第一层间介电层,覆盖所述硅化物挡层;一第二层间介电层,直接位于所述第一层间介电层上;一源极接触,在所述源极区上,所述源极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述源极接触包括在所述第一层间介电层中的第一掺杂多晶硅插塞,设置在所述第一掺杂多晶硅插塞上的第一自对准硅化物层,以及在所述第二层间介电层中和在所述第一自对准硅化物层上的第一导电金属层;以及一漏极接触,在所述漏极区上,所述漏极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述漏极接触包括在所述第一层间介电层中的第二掺杂多晶硅插塞,设置在所述第二掺杂多晶硅插塞上的第二自对准硅化物层,以及在所述第二层间介电层中和在所述第二自对准硅化物层上的第二导电金属层。
依据本发明实施例,其中,所述第一掺杂多晶硅插塞与所述源极区直接接触,所述第二掺杂多晶硅插塞与所述漏极区直接接触。
依据本发明实施例,其中,所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞包含N+掺杂多晶硅。
依据本发明实施例,其中,所述第一自对准硅化物层与所述第二自对准硅化物层位于同一平面上。
依据本发明实施例,所述半导体影像感测元件另包含:一栅极接触,位于所述栅极上,所述栅极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述栅极接触包括在所述第一层间介电层中的第三掺杂多晶硅插塞、设置在所述第三掺杂多晶硅插塞上的第三自对准硅化物层,以及在所述第二层间介电层中和在所述第三自对准硅化物层上的第三导电金属层。
依据本发明实施例,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层在同一平面上。
依据本发明实施例,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层包含硅化钛、硅化钴、硅化镍或硅化钨。
依据本发明实施例,其中,所述第一导电金属层、所述第二导电金属层和所述第三导电金属层包含钨、铝、钛、氮化钛、钽或氮化钽。
依据本发明实施例,其中,在所述栅极正上方的所述第一层间介电层的厚度小于300埃。
依据本发明实施例,其中,所述硅化物挡层包含氧化硅层。
本发明另一方面提供一种制作半导体影像感测元件的方法,包含:提供一半导体基底,其包含一影像感测像素区;在所述半导体基底上的所述影像感测像素区内形成一MOS晶体管,其中所述MOS晶体管包含一源极区、一与所述源极区区隔开的漏极区、一介于所述源极区和所述漏极区的通道区,以及一位于所述通道区上的栅极;形成一硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;形成一第一层间介电层,覆盖所述硅化物挡层;分别在所述源极区和所述漏极区上的所述第一层间介电层中形成第一掺杂多晶硅插塞和第二掺杂多晶硅插塞;在所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞上分别形成第一自对准硅化物层和第二自对准硅化物层;直接在所述第一层间介电层上形成第二层间介电层,并覆盖所述第一自对准硅化物层和所述第二自对准硅化物层;以及于所述第一自对准硅化物层和所述第二自对准硅化物层上的所述第二层间介电层中分别形成第一导电金属层和第二导电金属层。
依据本发明实施例,其中,所述第一掺杂多晶硅插塞与所述源极区直接接触,所述第二掺杂多晶硅插塞与所述漏极区直接接触。
依据本发明实施例,其中,所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞包含N+掺杂多晶硅。
依据本发明实施例,其中,所述第一自对准硅化物层与所述第二自对准硅化物层位于同一平面上。
依据本发明实施例,所述方法另包含:在所述栅极上形成一栅极接触,所述栅极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述栅极接触包括在所述第一层间介电层中的第三掺杂多晶硅插塞、设置在所述第三掺杂多晶硅插塞上的第三自对准硅化物层,以及在所述第二层间介电层中和在所述第三自对准硅化物层上的第三导电金属层。
依据本发明实施例,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层在同一平面上。
依据本发明实施例,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层包含硅化钛、硅化钴、硅化镍或硅化钨。
依据本发明实施例,其中,所述第一导电金属层、所述第二导电金属层和所述第三导电金属层包含钨、铝、钛、氮化钛、钽或氮化钽。
依据本发明实施例,其中,所述硅化物挡层包含氧化硅层。
本发明有另一方面提供一种半导体影像感测元件,包含:一半导体基底,包含一影像感测像素区;一MOS晶体管,设置于所述半导体基底上的所述影像感测像素区内,其中所述MOS晶体管包含一源极区、一与所述源极区区隔开的漏极区、一介于所述源极区和所述漏极区的通道区,以及一位于所述通道区上的栅极;一硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;一第一层间介电层,覆盖所述硅化物挡层;一第二层间介电层,直接位于所述第一层间介电层上;一源极接触,在所述源极区上,所述源极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述源极接触包括在所述第一层间介电层中的第一掺杂多晶硅插塞以及在所述第二层间介电层中的第一导电金属层;以及一漏极接触,在所述漏极区上,所述漏极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述漏极接触包括在所述第一层间介电层中的第二掺杂多晶硅插塞以及在所述第二层间介电层中的第二导电金属层。
附图说明
图1至图8为本发明实施例所绘示的制作半导体影像感测元件的方法剖面示意图;
图9为本发明另一实施例所绘示的半导体影像感测元件的剖面示意图。
主要元件符号说明
1半导体影像感测元件
100半导体基底
101影像感测像素区(像素区)
102逻辑电路区
110_P栅极介电层
110_L栅极介电层
111硅化物挡层
112、113层间介电层
121、122、123接触洞
130掺杂多晶硅层
131、132、133掺杂多晶硅插塞
141、142、143自对准硅化物层
151、152、153接触洞
161、162、163导电金属层
T1、T2 MOS晶体管
G1、G2栅极
S1、S2源极区
D1、D2漏极区
CH1、CH2通道区
SP1、SP2间隙壁
SAC_GL、SAC_SL、SAC_DL自对准硅化物层
C_GL、C_SL、C_DL接触洞
CT_GL、CT_SL、CT_DL导电金属层
CT_GP、CT_SP、CT_DP混合式栅极接触
t厚度
具体实施方式
在下文中,将参照附图说明细节,该些附图中的内容也构成说明书细节描述的一部分,并且以可实行该实施例的特例描述方式来绘示。下文实施例已描述足够的细节使该领域的一般技术人士得以据以实施。
当然,也可采行其他的实施例,或是在不悖离文中所述实施例的前提下作出任何结构性、逻辑性、及电性上的改变。因此,下文的细节描述不应被视为是限制,反之,其中所包含的实施例将由随附的权利要求来加以界定。
请参阅图1至图8,其为依据本发明实施例所绘示的制作半导体影像感测元件的方法剖面示意图。如图1所示,首先提供一半导体基底100,例如,硅基底,但不限于此。在半导体基底100上包含一影像感测像素区(以下简称像素区)101和一逻辑电路区102。在像素区101内已形成有金属-氧化物-半导体(metal-oxide-semiconductor,MOS)晶体管T1,包含栅极G1、源极区S1和漏极区D1。介于源极区S1和漏极区D1之间是通道区CH1,而栅极G1位于通道区CH1上。在逻辑电路区102内已形成有MOS晶体管T2,包含栅极G2、源极区S2和漏极区D2。介于源极区S2和漏极区D2之间是通道区CH2,而栅极G2位于通道区CH2上。
依据本发明实施例,在MOS晶体管T1的栅极G1和半导体基底100之间形成有栅极介电层110_P。在MOS晶体管T2的栅极G2和半导体基底100之间形成有栅极介电层110_L。依据本发明实施例,在MOS晶体管T1的栅极G1的侧壁上可以形成有间隙壁SP1,在MOS晶体管T2的栅极G2的侧壁上可以形成有间隙壁SP2。
依据本发明实施例,在逻辑电路区102内的MOS晶体管T2的栅极G2、源极区S2和漏极区D2上已分别形成有自对准硅化物层SAC_GL、自对准硅化物层SAC_SL和自对准硅化物层SAC_DL。值得注意的是,现阶段仅在逻辑电路区102内形成自对准硅化物层,而在像素区101内的MOS晶体管T1,包含栅极G1、源极区S1和漏极区D1上均未形成任何的自对准硅化物层,如此一来,可以避免金属污染,并降低暗电流。
自对准硅化物制作工艺首先是在已形成有半导体元件(例如晶体管)的晶片上沉积薄金属层,例如,钛、钴、镍等。接着,加热晶片,使金属与半导体元件的主动(有源)区(例如,源极区、漏极区和栅极)中的裸露的硅反应,形成低电阻的金属硅化物。金属不会与晶片上存在的氧化硅和/或氮化物绝缘层发生反应。反应后,通过化学蚀刻去除任何残留的金属,仅在元件的主动区中留下硅化物接触。
在针对逻辑电路区102内的MOS晶体管T2的栅极G2、源极区S2和漏极区D2进行上述自对准硅化制作工艺之前,需先在像素区101形成一硅化物挡层111,例如,氧化硅或氮化硅,覆盖MOS晶体管T1。完成逻辑电路区102内的MOS晶体管T2的栅极G2、源极区S2和漏极区D2上的自对准硅化物层SAC_GL、自对准硅化物层SAC_SL和自对准硅化物层SAC_DL之后,接着沉积一层间介电层112。层间介电层112覆盖像素区101和逻辑电路区102。在像素区101内,层间介电层112是覆盖在硅化物挡层111上。层间介电层112可以是硅氧层或者低介电常数材料层,但不限于此。依据本发明实施例,在栅极G1正上方的层间介电层112的厚度t可以小于300埃(angstrom),例如,200~300埃,但不限于此。
如图2所示,接着进行光刻制作工艺和蚀刻制作工艺,分别在像素区101内的MOS晶体管T1的栅极G1、源极区S1和漏极区D1上的层间介电层112中形成接触洞121、接触洞122和接触洞123。其中,接触洞121贯穿层间介电层112和硅化物挡层111,显露出部分的栅极G1,接触洞122贯穿层间介电层112和硅化物挡层111,显露出部分的源极区S1,接触洞123贯穿层间介电层112和硅化物挡层111,显露出部分的漏极区D1。此时,在逻辑电路区102内的MOS晶体管T2的栅极G2、源极区S2和漏极区D2上的层间介电层112中并未形成接触洞。
接着,如图3所示,在半导体基底100上沉积一掺杂多晶硅层130,例如,N+掺杂多晶硅层,使掺杂多晶硅层130填满像素区101内的接触洞121、接触洞122和接触洞123。依据本发明实施例,掺杂多晶硅层130可以利用化学气相沉积制作工艺等方法形成,但不限于此。
如图4所示,接着进行一化学机械研磨(chemical mechanical polisging,CMP)制作工艺,研磨掉在层间介电层112上方多余的掺杂多晶硅层130,如此分别接触洞121、接触洞122和接触洞123中形成掺杂多晶硅插塞131、掺杂多晶硅插塞132和掺杂多晶硅插塞133。掺杂多晶硅插塞131与栅极G1直接接触,掺杂多晶硅插塞132与源极区S1直接接触,掺杂多晶硅插塞133与漏极区D1直接接触。此时,掺杂多晶硅插塞131、掺杂多晶硅插塞132和掺杂多晶硅插塞133的上表面与层间介电层112的上表面齐平。
如图5所示,接着针对像素区101进行自对准硅化物制作工艺,在显露出的掺杂多晶硅插塞131、掺杂多晶硅插塞132和掺杂多晶硅插塞133的上表面分别形成自对准硅化物层141、自对准硅化物层142和自对准硅化物层143。依据本发明实施例,自对准硅化物层141、自对准硅化物层142和自对准硅化物层143在同一平面上。依据本发明实施例,自对准硅化物层141、自对准硅化物层142和自对准硅化物层143包含硅化钛、硅化钴、硅化镍或硅化钨。
如图6所示,接着直接在层间介电层112上形成层间介电层113,并覆盖自对准硅化物层141、自对准硅化物层142和自对准硅化物层143。层间介电层113可以是硅氧层或者低介电常数材料层,但不限于此。依据本发明实施例,层间介电层113的厚度大于层间介电层112的厚度。
如图7所示,接着进行光刻制作工艺和蚀刻制作工艺,分别在像素区101内的MOS晶体管T1的栅极G1、源极区S1和漏极区D1上的层间介电层113中形成接触洞151、接触洞152和接触洞153。其中,接触洞151贯穿层间介电层113,显露出部分的自对准硅化物层141,接触洞152贯穿层间介电层113,显露出部分的自对准硅化物层142,接触洞153贯穿层间介电层113,显露出部分的自对准硅化物层143。此外,同时在逻辑电路区102内的MOS晶体管T2的自对准硅化物层SAC_GL、自对准硅化物层SAC_SL和自对准硅化物层SAC_DL上的层间介电层113和层间介电层112中分别形成接触洞C_GL、接触洞C_SL和接触洞C_DL。
最后,如图8所示,在像素区101内的接触洞151、接触洞152和接触洞153中分别形成导电金属层161、导电金属层162和导电金属层163。同时,在逻辑电路区102内的接触洞C_GL、接触洞C_SL和接触洞C_DL中分别形成导电金属层CT_GL、导电金属层CT_SL和导电金属层CT_DL。其中,在像素区101内,导电金属层161、自对准硅化物层141和掺杂多晶硅插塞131构成一混合式(hybrid)栅极接触CT_GP,导电金属层162、自对准硅化物层142和掺杂多晶硅插塞132构成一混合式源极接触CT_SP,导电金属层163、自对准硅化物层143和掺杂多晶硅插塞133构成一混合式漏极接触CT_DP。依据本发明实施例,导电金属层161、导电金属层162和导电金属层163包含钨、铝、钛、氮化钛、钽或氮化钽。
结构上,如图8所示,本发明半导体影像感测元件1包含:半导体基底100,包含影像感测像素区101;MOS晶体管T1,设置于半导体基底100上的影像感测像素区101内,其中MOS晶体管T1包含源极区S1、与源极区S1区隔开的漏极区D1、介于源极区S1和漏极区D1的通道区CH1,以及位于通道区CH1上的栅极G1;硅化物挡层111,覆盖MOS晶体管T1和影像感测像素区101;层间介电层112,覆盖硅化物挡层111;层间介电层113,直接位于层间介电层112上;源极接触CT_SP,在源极区S1上,其中源极接触CT_SP延伸穿过层间介电层113、层间介电层112和硅化物挡层111,且源极接触CT_SP包括在层间介电层112中的掺杂多晶硅插塞132,设置在掺杂多晶硅插塞132上的自对准硅化物层142,以及在层间介电层113中和在自对准硅化物层142上的导电金属层162;以及漏极接触CT_DP,在漏极区D1上,漏极接触CT_DP延伸穿过层间介电层113、层间介电层112和硅化物挡层111,且漏极接触CT_DP包括在层间介电层112中的掺杂多晶硅插塞133,设置在掺杂多晶硅插塞133上的自对准硅化物层143,以及在层间介电层113中和在自对准硅化物层143上的导电金属层163。
依据本发明实施例,其中,掺杂多晶硅插塞132与源极区S1直接接触,掺杂多晶硅插塞133与漏极区D1直接接触。依据本发明实施例,其中,掺杂多晶硅插塞132和掺杂多晶硅插塞133包含N+掺杂多晶硅。
依据本发明实施例,其中,所自对准硅化物层142与自对准硅化物层143位于同一平面上。
依据本发明实施例,本发明半导体影像感测元件1另包含:栅极接触CT_GP,位于栅极G1上,栅极接触CT_GP延伸穿过层间介电层113、层间介电层112和硅化物挡层111,且栅极接触CT_GP包括在层间介电层112中的掺杂多晶硅插塞131、设置在掺杂多晶硅插塞131上的自对准硅化物层141,以及在层间介电层113中和在自对准硅化物层141上的导电金属层161。
依据本发明实施例,其中,自对准硅化物层141、自对准硅化物层142和自对准硅化物层143在同一平面上。依据本发明实施例,其中,自对准硅化物层141、自对准硅化物层142和自对准硅化物层143包含硅化钛、硅化钴、硅化镍或硅化钨。
依据本发明实施例,其中,导电金属层161、导电金属层162和导电金属层163包含钨、铝、钛、氮化钛、钽或氮化钽。
依据本发明实施例,其中,在栅极G1正上方的层间介电层112的厚度小于300埃。
依据本发明实施例,其中,硅化物挡层111包含氧化硅层。
请参阅图9,其为依据本发明另一实施例所绘示的半导体影像感测元件的剖面示意图。图9中的半导体影像感测元件的结构与图8中的结构大致上相同,差异在于图9中的半导体影像感测元件的栅极接触CT_GP、源极接触CT_SP和漏极接触CT_DP中,不包含自对准硅化物层。如图9所示,栅极接触CT_GP的导电金属层161直接接触掺杂多晶硅插塞131,源极接触CT_SP的导电金属层162直接接触掺杂多晶硅插塞132,漏极接触CT_DP的导电金属层163直接接触掺杂多晶硅插塞133。
以上所述仅为本发明的优选实施例,凡依本发明权利要求所做的均等变化与修饰,都应属本发明的涵盖范围。
Claims (20)
1.一种半导体影像感测元件,其特征在于,包含:
半导体基底,包含影像感测像素区;
MOS晶体管,设置于所述半导体基底上的所述影像感测像素区内,其中所述MOS晶体管包含源极区、与所述源极区区隔开的漏极区、介于所述源极区和所述漏极区的通道区,以及位于所述通道区上的栅极;
硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;
第一层间介电层,覆盖所述硅化物挡层;
第二层间介电层,直接位于所述第一层间介电层上;
源极接触,在所述源极区上,所述源极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述源极接触包括在所述第一层间介电层中的第一掺杂多晶硅插塞、设置在所述第一掺杂多晶硅插塞上的第一自对准硅化物层,以及在所述第二层间介电层中和在所述第一自对准硅化物层上的第一导电金属层;以及
漏极接触,在所述漏极区上,所述漏极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述漏极接触包括在所述第一层间介电层中的第二掺杂多晶硅插塞、设置在所述第二掺杂多晶硅插塞上的第二自对准硅化物层,以及在所述第二层间介电层中和在所述第二自对准硅化物层上的第二导电金属层。
2.如权利要求1所述的半导体影像感测元件,其中,所述第一掺杂多晶硅插塞与所述源极区直接接触,所述第二掺杂多晶硅插塞与所述漏极区直接接触。
3.如权利要求1所述的半导体影像感测元件,其中,所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞包含N+掺杂多晶硅。
4.如权利要求1所述的半导体影像感测元件,其中,所述第一自对准硅化物层与所述第二自对准硅化物层位于同一平面上。
5.如权利要求4所述的半导体影像感测元件,其中另包含:
栅极接触,位于所述栅极上,所述栅极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述栅极接触包括在所述第一层间介电层中的第三掺杂多晶硅插塞、设置在所述第三掺杂多晶硅插塞上的第三自对准硅化物层,以及在所述第二层间介电层中和在所述第三自对准硅化物层上的第三导电金属层。
6.如权利要求5所述的半导体影像感测元件,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层在同一平面上。
7.如权利要求5所述的半导体影像感测元件,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层包含硅化钛、硅化钴、硅化镍或硅化钨。
8.如权利要求5所述的半导体影像感测元件,其中,所述第一导电金属层、所述第二导电金属层和所述第三导电金属层包含钨、铝、钛、氮化钛、钽或氮化钽。
9.如权利要求1所述的半导体影像感测元件,其中,在所述栅极正上方的所述第一层间介电层的厚度小于300埃。
10.如权利要求1所述的半导体影像感测元件,其中,所述硅化物挡层包含氧化硅层。
11.一种制作半导体影像感测元件的方法,包含:
提供半导体基底,其包含影像感测像素区;
在所述半导体基底上的所述影像感测像素区内形成MOS晶体管,其中所述MOS晶体管包含源极区、与所述源极区区隔开的漏极区、介于所述源极区和所述漏极区的通道区,以及位于所述通道区上的栅极;
形成硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;
形成第一层间介电层,覆盖所述硅化物挡层;
分别在所述源极区和所述漏极区上的所述第一层间介电层中形成第一掺杂多晶硅插塞和第二掺杂多晶硅插塞;
在所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞上分别形成第一自对准硅化物层和第二自对准硅化物层;
直接在所述第一层间介电层上形成第二层间介电层,并覆盖所述第一自对准硅化物层和所述第二自对准硅化物层;以及
在所述第一自对准硅化物层和所述第二自对准硅化物层上的所述第二层间介电层中分别形成第一导电金属层和第二导电金属层。
12.如权利要求11所述的方法,其中,所述第一掺杂多晶硅插塞与所述源极区直接接触,所述第二掺杂多晶硅插塞与所述漏极区直接接触。
13.如权利要求11所述的方法,其中,所述第一掺杂多晶硅插塞和所述第二掺杂多晶硅插塞包含N+掺杂多晶硅。
14.如权利要求11所述的方法,其中,所述第一自对准硅化物层与所述第二自对准硅化物层位于同一平面上。
15.如权利要求14所述的方法,其中另包含:
在所述栅极上形成栅极接触,所述栅极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述栅极接触包括在所述第一层间介电层中的第三掺杂多晶硅插塞、设置在所述第三掺杂多晶硅插塞上的第三自对准硅化物层,以及在所述第二层间介电层中和在所述第三自对准硅化物层上的第三导电金属层。
16.如权利要求15所述的方法,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层在同一平面上。
17.如权利要求15所述的方法,其中,所述第一自对准硅化物层、所述第二自对准硅化物层和所述第三自对准硅化物层包含硅化钛、硅化钴、硅化镍或硅化钨。
18.如权利要求15所述的方法,其中,所述第一导电金属层、所述第二导电金属层和所述第三导电金属层包含钨、铝、钛、氮化钛、钽或氮化钽。
19.如权利要求11所述的方法,其中,所述硅化物挡层包含氧化硅层。
20.一种半导体影像感测元件,其特征在于,包含:
半导体基底,包含影像感测像素区;
MOS晶体管,设置于所述半导体基底上的所述影像感测像素区内,其中所述MOS晶体管包含源极区、与所述源极区区隔开的漏极区、介于所述源极区和所述漏极区的通道区,以及位于所述通道区上的栅极;
硅化物挡层,覆盖所述MOS晶体管和所述影像感测像素区;
第一层间介电层,覆盖所述硅化物挡层;
第二层间介电层,直接位于所述第一层间介电层上;
源极接触,在所述源极区上,所述源极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述源极接触包括在所述第一层间介电层中的第一掺杂多晶硅插塞以及在所述第二层间介电层中的第一导电金属层;以及
漏极接触,在所述漏极区上,所述漏极接触延伸穿过所述第二层间介电层、所述第一层间介电层和所述硅化物挡层,且所述漏极接触包括在所述第一层间介电层中的第二掺杂多晶硅插塞以及在所述第二层间介电层中的第二导电金属层。
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Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010402A1 (en) * | 2000-01-25 | 2001-08-02 | Nec Corporation | Semiconductor device structure and method for manufacturing the same |
US6303406B1 (en) * | 2000-06-08 | 2001-10-16 | United Microelectronics Corp. | Method for integrating anti-reflection layer and salicide block |
US20050045924A1 (en) * | 2003-08-26 | 2005-03-03 | Tigelaar Howard Lee | Low resistance integrated circuit MOS transistor |
US20070001235A1 (en) * | 2005-06-29 | 2007-01-04 | Micron Technology, Inc. | Buried conductor for imagers |
US20070241375A1 (en) * | 2006-04-17 | 2007-10-18 | Jhy-Jyi Sze | Image sensor and method of forming the same |
US20080128823A1 (en) * | 2006-11-30 | 2008-06-05 | Shinji Takeoka | Semiconductor device and method for fabricating the same |
US20140332868A1 (en) * | 2013-05-09 | 2014-11-13 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
US20150076500A1 (en) * | 2012-06-21 | 2015-03-19 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device and method for manufacturing the same |
CN107946332A (zh) * | 2017-11-22 | 2018-04-20 | 德淮半导体有限公司 | 半导体结构、cmos图像传感器及其制备方法 |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5291058A (en) * | 1989-04-19 | 1994-03-01 | Kabushiki Kaisha Toshiba | Semiconductor device silicon via fill formed in multiple dielectric layers |
US6287951B1 (en) * | 1998-12-07 | 2001-09-11 | Motorola Inc. | Process for forming a combination hardmask and antireflective layer |
US20010053572A1 (en) * | 2000-02-23 | 2001-12-20 | Yoshinari Ichihashi | Semiconductor device having opening and method of fabricating the same |
US6448595B1 (en) * | 2000-06-26 | 2002-09-10 | Twin Han Technology Co., Ltd. | Active photodiode CMOS image sensor structure |
JP2002319632A (ja) * | 2001-04-20 | 2002-10-31 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
JP2002324850A (ja) * | 2001-04-25 | 2002-11-08 | Mitsubishi Electric Corp | 半導体メモリ装置およびその製造方法 |
US6635576B1 (en) * | 2001-12-03 | 2003-10-21 | Taiwan Semiconductor Manufacturing Company | Method of fabricating borderless contact using graded-stair etch stop layers |
KR100492155B1 (ko) * | 2002-08-08 | 2005-06-01 | 삼성전자주식회사 | 반도체 소자의 실리사이드막 형성방법 |
KR100953332B1 (ko) * | 2002-12-31 | 2010-04-20 | 동부일렉트로닉스 주식회사 | 반도체 장치의 제조 방법 |
US6897504B2 (en) * | 2003-03-31 | 2005-05-24 | Taiwan Semiconductor Manufacturing | Salicided MOS device and one-sided salicided MOS device, and simultaneous fabrication method thereof |
US7329953B2 (en) * | 2003-10-29 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same |
US7064067B1 (en) * | 2004-02-02 | 2006-06-20 | Advanced Micro Devices, Inc. | Reduction of lateral silicide growth in integrated circuit technology |
JP4530747B2 (ja) * | 2004-07-16 | 2010-08-25 | 富士通セミコンダクター株式会社 | 固体撮像装置及びその製造方法 |
US20060228843A1 (en) * | 2005-04-12 | 2006-10-12 | Alex Liu | Method of fabricating semiconductor devices and method of adjusting lattice distance in device channel |
US7732289B2 (en) * | 2005-07-05 | 2010-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming a MOS device with an additional layer |
US8164141B2 (en) * | 2005-10-06 | 2012-04-24 | United Microelectronics Corp. | Opening structure with sidewall of an opening covered with a dielectric thin film |
US20070131988A1 (en) | 2005-12-12 | 2007-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | CMOS image sensor devices and fabrication method thereof |
JP2007214538A (ja) * | 2006-01-11 | 2007-08-23 | Renesas Technology Corp | 半導体装置およびその製造方法 |
JP5110820B2 (ja) * | 2006-08-02 | 2012-12-26 | キヤノン株式会社 | 光電変換装置、光電変換装置の製造方法及び撮像システム |
US7709903B2 (en) * | 2007-05-25 | 2010-05-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact barrier structure and manufacturing methods |
US7863176B2 (en) * | 2008-05-13 | 2011-01-04 | Micron Technology, Inc. | Low-resistance interconnects and methods of making same |
US8247262B2 (en) * | 2009-05-04 | 2012-08-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for reducing contact resistance of CMOS image sensor |
US20110027950A1 (en) * | 2009-07-28 | 2011-02-03 | Jones Robert E | Method for forming a semiconductor device having a photodetector |
US8358012B2 (en) * | 2010-08-03 | 2013-01-22 | International Business Machines Corporation | Metal semiconductor alloy structure for low contact resistance |
KR101776926B1 (ko) * | 2010-09-07 | 2017-09-08 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR101716113B1 (ko) * | 2010-11-03 | 2017-03-15 | 삼성전자 주식회사 | 반도체 소자 및 이의 제조 방법 |
US9406614B2 (en) * | 2013-03-08 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Material and process for copper barrier layer |
US9269809B2 (en) * | 2013-03-14 | 2016-02-23 | Globalfoundries Inc. | Methods for forming protection layers on sidewalls of contact etch stop layers |
US9209272B2 (en) * | 2013-09-11 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Oxidation and etching post metal gate CMP |
JP2015109343A (ja) * | 2013-12-04 | 2015-06-11 | キヤノン株式会社 | 半導体装置の製造方法 |
JP6282109B2 (ja) * | 2013-12-26 | 2018-02-21 | キヤノン株式会社 | 撮像装置の製造方法および撮像装置 |
JP6249888B2 (ja) * | 2014-06-19 | 2017-12-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US9870943B2 (en) * | 2015-01-16 | 2018-01-16 | Macronix International Co., Ltd. | Contact process and contact structure for semiconductor device |
US9431253B1 (en) * | 2015-08-05 | 2016-08-30 | Texas Instruments Incorporated | Fabrication flow based on metal gate process for making low cost flash memory |
KR102452290B1 (ko) * | 2015-09-04 | 2022-12-01 | 에스케이하이닉스 주식회사 | 반도체구조물 및 그 제조 방법 |
JP6617045B2 (ja) * | 2016-02-02 | 2019-12-04 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
US9917009B2 (en) * | 2016-08-04 | 2018-03-13 | Globalfoundries Inc. | Methods of forming a through-substrate-via (TSV) and a metallization layer after formation of a semiconductor device |
JP6808481B2 (ja) * | 2016-12-27 | 2021-01-06 | キヤノン株式会社 | 半導体装置、システム、および、半導体装置の製造方法 |
US10170376B1 (en) * | 2017-10-22 | 2019-01-01 | United Microelectronics Corp. | Device and forming method thereof |
US11417749B2 (en) * | 2019-06-14 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement with airgap and method of forming |
CN112397531B (zh) * | 2019-08-13 | 2024-07-23 | 联华电子股份有限公司 | 半导体元件及其制造方法 |
US11444087B2 (en) * | 2020-04-24 | 2022-09-13 | Nanya Technology Corporation | Semiconductor memory device with air gaps for reducing capacitive coupling and method for preparing the same |
-
2020
- 2020-01-15 CN CN202010040976.7A patent/CN113130516A/zh active Pending
- 2020-02-19 US US16/794,233 patent/US11538844B2/en active Active
- 2020-05-14 EP EP20174718.5A patent/EP3852143A1/en active Pending
-
2022
- 2022-11-21 US US17/990,755 patent/US11881493B2/en active Active
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20010010402A1 (en) * | 2000-01-25 | 2001-08-02 | Nec Corporation | Semiconductor device structure and method for manufacturing the same |
US6303406B1 (en) * | 2000-06-08 | 2001-10-16 | United Microelectronics Corp. | Method for integrating anti-reflection layer and salicide block |
US20050045924A1 (en) * | 2003-08-26 | 2005-03-03 | Tigelaar Howard Lee | Low resistance integrated circuit MOS transistor |
US20070001235A1 (en) * | 2005-06-29 | 2007-01-04 | Micron Technology, Inc. | Buried conductor for imagers |
US20070241375A1 (en) * | 2006-04-17 | 2007-10-18 | Jhy-Jyi Sze | Image sensor and method of forming the same |
US20080128823A1 (en) * | 2006-11-30 | 2008-06-05 | Shinji Takeoka | Semiconductor device and method for fabricating the same |
US20150076500A1 (en) * | 2012-06-21 | 2015-03-19 | Panasonic Intellectual Property Management Co., Ltd. | Solid-state imaging device and method for manufacturing the same |
US20140332868A1 (en) * | 2013-05-09 | 2014-11-13 | United Microelectronics Corp. | Semiconductor device and manufacturing method thereof |
CN107946332A (zh) * | 2017-11-22 | 2018-04-20 | 德淮半导体有限公司 | 半导体结构、cmos图像传感器及其制备方法 |
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