CN107924921A - 基于金属栅极工艺的低成本闪速存储器制造流程 - Google Patents

基于金属栅极工艺的低成本闪速存储器制造流程 Download PDF

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CN107924921A
CN107924921A CN201680045464.1A CN201680045464A CN107924921A CN 107924921 A CN107924921 A CN 107924921A CN 201680045464 A CN201680045464 A CN 201680045464A CN 107924921 A CN107924921 A CN 107924921A
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source
sensing
drain
layer
metal
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CN107924921B (zh
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N·谭
W·田
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

在所描述的示例中，集成电路(100)包含闪速单元(106)，其中感测晶体管(108)的顶部栅极(136)是在浮栅(130)上方的金属感测栅极(106)。感测晶体管(108)的源极/漏极区(138)在浮栅(130)下方延伸使得源极区与漏极区隔开小于200纳米的感测沟道长度(126)。浮栅(130)的宽度至少为400纳米，则感测晶体管(108)的源极/漏极区(138)在浮栅(130)下方在每侧上延伸至少100纳米。在形成浮栅(130)之前，通过形成感测晶体管源极区和漏极区(138)来形成集成电路(100)。

Description

基于金属栅极工艺的低成本闪速存储器制造流程
技术领域
本发明总体涉及集成电路，并且更具体地涉及集成电路中的闪速存储器单元。
背景技术
集成电路包含闪速存储器单元，其中感测晶体管的顶部栅极是在浮栅上方的金属板。可以利用添加一个额外的光刻操作将该闪速单元集成到互补金属氧化物半导体(CMOS)制造流程中。顶部栅极通过底切金属板的湿法蚀刻工艺形成，要求浮栅过大。由于热载流子注入的增加，使浮栅过大可能导致闪速单元的可靠性问题。过大的浮栅要求大的横向场用于有效的热载流子注入编程(programming)。对于某一工艺，所要求的值在物理上是不可能实现的。为了在低漏极电压(例如小于6伏特)处实现有效的HCI编程，沟道长度必须被较小。
发明内容
在所描述的示例中，集成电路包含闪速单元，其中感测晶体管的顶部栅极是在浮栅上方的金属感测栅极。感测晶体管的源极/漏极区在浮栅下方延伸使得源极区域与漏极区域隔开小于200纳米的感测沟道长度。金属感测栅极不在源极区域和漏极区域的上方延伸穿过浮栅。浮栅的宽度至少为400纳米，所以感测晶体管的源极/漏极区在浮栅下方在每侧上延伸至少100纳米。在形成浮栅之前，通过形成感测晶体管的源极区域和漏极区域来形成集成电路。
附图说明
图1是示例集成电路的截面。
图2A至图2J是在示例制造序列的连续阶段中描绘的图1的集成电路的截面。
具体实施方式
附图未按比例绘制。有些行为可以以不同的顺序发生和/或与其它行为或事件同时发生。此外，不是所有图示说明的行为或事件被要求实施根据示例实施例的方法。
集成电路包含闪速单元，其中感测晶体管的顶部栅极是在浮栅上方的金属感测栅极。感测晶体管的源极/漏极区在浮栅下方部分地(partway)延伸，使得源极区域与漏极区域隔开小于200纳米的感测沟道长度。金属感测栅极不在源极区域和漏极区域上方延伸穿过浮栅。浮栅的宽度为至少400纳米，所以感测晶体管的源极/漏极区在浮栅下方在每侧上延伸至少100纳米。在形成浮栅之前，通过形成感测晶体管的源极区域和漏极区域来形成集成电路。
图1是示例集成电路的截面。集成电路100形成在包含半导体材料104的衬底102上。例如，衬底102可以是单晶硅。半导体材料104也可以是单晶硅。在该示例中，半导体材料104是p型的。集成电路100包括闪速存储器106，闪速存储器106具有至少一个感测晶体管108并且可以具有存取晶体管110。在该示例中，感测晶体管108和存取晶体管110是n沟道金属氧化物半导体(NMOS)晶体管。集成电路100还可以包括与闪速存储器106分开的至少一个逻辑NMOS晶体管112。场氧化物114被设置在衬底102的顶表面116处以横向隔离集成电路100的组件。感测晶体管108和存取晶体管110被设置在衬底102中的隔离的p型阱118中。隔离的p型阱118由设置在隔离的p型阱118下方的衬底102中的深n型阱120和横向围绕隔离的p型阱118的n型阱122的组合电隔离。逻辑NMOS晶体管112被设置在与衬底102的p型半导体材料104接触的p型阱124中。
感测晶体管108包括在隔离的p型阱118中的衬底102的顶表面116上的具有厚度128的栅极介电层126，以及在栅极介电层126上的具有宽度132的浮栅130。栅极介电层126的厚度128小于3.0纳米，并且可以是1.5纳米至2.5纳米。例如，浮栅130可以是多晶的硅，在本文中称为多晶硅。宽度132至少为400纳米。顶部栅极介电层134被设置在浮栅130的上方，跨越浮栅130的宽度132延伸，并且金属感测栅极136被设置在顶部栅极介电层134的上方。金属感测层136不在感测晶体管108的源极和漏极侧上延伸穿过浮栅130。例如，金属感测栅极136可以是40纳米至80纳米厚。N型感测源极/漏极区138被设置在隔离的p型阱118中，在浮栅130下方部分地延伸。感测源极/漏极区138由在浮栅130下方的感测沟道长度140隔开；感测沟道长度140小于200纳米，使得感测源极/漏极区138在浮栅130下方在感测晶体管108的每个源极和漏极侧上延伸至少100纳米。例如，可比较的逻辑晶体管的源极/漏极区可以在对应的逻辑栅极下方在每个源极和漏极侧上延伸小于25纳米。感测源极/漏极区138可以包括设置在浮栅130外侧(outward)的深源极/漏极部分142。偏移间隔件144被设置在浮栅130的侧壁上并且源极/漏极侧壁间隔件146被设置在偏移间隔件144上。
存取晶体管110包含设置在隔离的p型阱118中的衬底102的顶表面116上的栅极介电层148和在栅极介电层148上的栅极150。栅极介电层148具有与感测晶体管108的栅极介电层126相同的组分(composition)和厚度。栅极150具有与感测晶体管108的浮栅130相同的组分。N型存取源极/漏极区152被设置在隔离的p型阱118中，在栅极150下方部分地延伸。存取源极/漏极区152在栅极150下方不像感测源极/漏极区138在浮栅130下方延伸得远。例如，存取源极/漏极区152可以在浮栅130下方延伸，延伸小于25纳米。存取源极/漏极区152包含设置在栅极150外侧的深源极/漏极部分154。存取晶体管110的深源极/漏极部分154具有与感测晶体管108的源极/漏极部分142类似的掺杂分布。如在图1中由幻线(phantomline)所指示，邻近感测晶体管108的存取源极/漏极区152与邻近存取晶体管110的感测源极/漏极区138是连续的。偏移间隔件156被设置在栅极150的侧壁上并且源极/漏极侧壁间隔件158被设置在偏移间隔件156上。
N型接触区160可以围绕感测晶体管108和存取晶体管110被设置在n型阱122中的衬底102的顶表面116处。接触区160可以具有与感测晶体管108的深源极/漏极部分142和存取晶体管110的深源极/漏极部分154类似的掺杂分布。
逻辑NMOS晶体管112包括设置在p型阱124中的衬底102的顶表面116上的栅极介电层162和在栅极介电层162上的栅极164。栅极介电层162具有与感测晶体管108的栅极介电层126相同的组分和厚度。栅极164具有与感测晶体管108的浮栅130相同的组分。N型逻辑源极/漏极区166被设置在p型阱124中，在栅极164下方部分地延伸。逻辑源极/漏极区166在栅极164下方延伸得不如感测源极/漏极区138在浮栅130下方延伸得那样远。逻辑源极/漏极区166包括设置在栅极164外侧的深源极/漏极部分168。逻辑NMOS晶体管112的深源极/漏极部分168具有与感测晶体管108的深源极/漏极部分142相似的掺杂分布。偏移间隔件170被设置在栅极164的侧壁上并且源极/漏极侧壁间隔件172被设置在偏移间隔件170上。
金属硅化物174可以被设置在裸露的硅(例如，感测晶体管108的深源极/漏极部分142，存取晶体管110的深源极/漏极部分154，n型阱122中的接触区160以及逻辑NMOS晶体管112的深源极/漏极部分168)上的衬底102的顶表面116处，并且可选地设置在存取晶体管110的栅极150上和逻辑NMOS晶体管112的栅极164上，金属硅化物174不被设置在感测晶体管108的浮栅130上。
前置金属介电(PMD)层176被设置在衬底102的顶表面116的上方并且被设置在金属硅化物174、感测晶体管108、存取晶体管110和逻辑NMOS晶体管112的上方。PMD层176可以是包含氮化硅的PMD衬垫、硼磷硅酸盐玻璃(BPSG)或二氧化硅的主层、以及氮化硅、碳化硅、碳化硅氮化物或适合用于钨化学机械抛光(CMP)工艺的停止层的其它硬介电材料的保护层的层堆叠。触点(contact)178被设置为穿过PMD层176以通过金属硅化物174提供到感测晶体管108、存取晶体管110和逻辑NMOS晶体管112的电气连接。触点178包含接触PMD层176的钛和氮化钛的接触衬垫180和在接触衬垫180上的钨的接触填充金属182。可以通过形成穿过PMD层176的接触孔，在接触孔的侧壁和底部上形成接触衬垫180，并且在接触衬垫180上形成接触填充金属182的层，并且随后(例如通过金属CMP工艺或回蚀工艺)从PMD层176的顶表面移除接触填充金属182和接触衬垫180来形成触点178。
金属间介电(IMD)层184被设置在PMD层176上。IMD层184可以包括碳化硅或碳化硅氮化物(silicon carbide nitride)的蚀刻停止层、二氧化硅或低k介电材料(例如有机硅酸盐玻璃(OSG)的主层、以及氮化硅、碳化硅、碳化硅氮化物或适合用于铜CMP工艺的停止层的其它硬介电材料的保护层。金属互连件186被设置穿过IMD层184以提供到触点178的电气连接。金属互连件186具有铜镶嵌结构，该结构具有邻接IMD层184并连接到触点178的氮化钽的沟槽衬垫188、以及在沟槽衬垫188上的铜填充金属190。金属互连件186可以通过铜镶嵌工艺形成，该铜镶嵌工艺包含穿过IMD层184形成互连沟槽，在互连沟槽的侧壁和底部上形成沟槽衬垫188，通过溅射在沟槽衬垫188上形成作为铜填充金属190的第一部分的铜种子层，通过电镀在铜种子层上形成作为铜填充金属190的第二部分的填充铜层，并且随后通过铜CMP工艺移除铜填充金属190和沟槽衬垫188。
感测晶体管108的金属感测栅极136可以具有类似于触点178的接触衬垫180或类似于金属互连件186的沟槽衬垫188的组分，并且可以以与诸如反应溅射工具或原子层沉积工具相同的工具形成。以与接触衬垫180或沟槽衬垫188相同的工具形成金属感测栅极136可以有利地降低集成电路100的制造成本。
在集成电路100的操作期间，由于在浮栅130下方的感测沟道长度140小于200纳米，感测晶体管108可以展现期望水平的可靠性。感测晶体管108可以具有显著小于1毫秒的编程时间和期望的低编程电压，因为浮栅130的宽度132至少为400纳米，使得在由于湿法蚀刻工艺的底切导致的宽度减小之后充足宽度能够用于金属感测栅极136以限定金属感测栅极136。数据保持和耐久性也可以显著地优于其中浮栅的长度小于300纳米的感测晶体管。
图2A至图2J是以示例制造序列的连续阶段描绘的图1的集成电路的截面。参考图2A，集成电路100形成在衬底102中和衬底102上。例如，衬底102可以是硅晶圆。半导体材料104可以是体硅晶圆的顶部，或者可以是在体硅晶圆上形成的外延层。例如，场氧化物114由浅沟槽隔离(STI)工艺形成。随后可以通过将n型掺杂剂(例如磷)植入衬底102来形成深n型阱120。例如，使用包含光刻胶的植入掩模的植入(在1000keV至1500keV的能量下以2×1012cm-2至5×1012cm-2的剂量)，可以在衬底102的顶表面116以下产生1微米至1.5微米的期望的峰值掺杂分布。可以通过使用包含光刻胶的植入掩模将p型掺杂剂(例如硼)植入到衬底102中(在250keV至350keV的能量下以5×1012cm-2至1×1013cm-2的剂量，所述植入在衬底102的顶表面116以下产生0.6微米至0.9微米的峰值掺杂分布)来形成隔离的p型阱118和p型阱124。可以同时植入附加的p型掺杂剂以形成用于感测晶体管108、存取晶体管110和逻辑NMOS晶体管112的穿通减小区(punch-through reduction region)和阈值调整区。可以通过使用包含光刻胶的植入掩模将n型掺杂剂(例如磷)植入到衬底102中(在400keV至600keV的能量下以5×1012cm-2至2×1013cm-2的剂量，所述植入在衬底102的顶表面116以下产生0.4微米至0.8微米的峰值掺杂分布)来形成n型阱122。随后衬底102被退火以激活植入的掺杂剂。
感测源极/漏极掩模192在衬底102的上方形成，其使在用于图1的感测源极/漏极区138的区域中的衬底102暴露。感测源极/漏极掩模192覆盖用于感测源极/漏极区138的区域之间的衬底102。感测源极/漏极掩模192可以可选地使用于n型源极/漏极区或接触区的其它区域暴露。N型掺杂剂194(例如磷和砷)被植入到由感测源极/漏极掩模192暴露的衬底102中(例如在30keV至70keV的能量下以5×1013cm-2至3×1014cm-2的总剂量)，从而在用于感测源极/漏极区138的区域中形成感测源极/漏极植入区196。随后例如通过灰化工艺接着通过湿法清洁工艺移除感测源极/漏极掩模192。
参考图2B，感测晶体管108、存取晶体管110和逻辑NMOS晶体管112各自的栅极介电层126、栅极介电层148和栅极介电层162同时形成。栅极介电层126、栅极介电层148和栅极介电层162可以通过热氧化形成并且可以可选地被氮化，例如通过暴露于含氮等离子体。栅极介电层126、栅极介电层148和栅极介电层162可以可选地包含诸如氧化铪或氧化锆的高k介电材料。在栅极介电层126、栅极介电层148和栅极介电层162的形成期间，在图2A的感测源极/漏极植入区196中的植入的掺杂剂可以至少部分地被激活以形成感测源极/漏极区138。
随后在栅极介电层126、栅极介电层148和栅极介电层162上分别同时形成感测晶体管108的浮栅130、存取晶体管110的栅极150和逻辑NMOS晶体管112的栅极164。例如，可以通过在栅极介电材料的公共层上形成150纳米至200纳米厚的多晶硅层、以1×1015cm-2至6×1015cm-2的总剂量将多晶硅层植入具有n型掺杂剂(例如磷和可能的砷)的用于n沟道晶体管的栅极的区域中来形成浮栅130、栅极150和栅极164。随后在多晶硅层的上方形成栅极蚀刻掩模以覆盖用于NMOS晶体管的栅极(包含浮栅130、栅极150和栅极164)和用于p沟道金属氧化物半导体(PMOS)晶体管的栅极的区域。通过反应离子蚀刻(RIE)工艺在由栅极蚀刻掩模暴露的区域中移除多晶硅层，留下的多晶硅以形成浮栅130、栅极150和栅极164。可以通过RIE工艺减小或移除栅极介电层126、栅极介电层148和栅极介电层162之外的栅极介电材料的公共层。
在浮栅130、栅极150和栅极164上形成(可能同时地)形成偏移间隔件144、偏移间隔件156和偏移间隔件170。偏移间隔件144、偏移间隔件156和偏移间隔件170可以包含热氧化物和可选的由等离子体增强化学气相沉积(PECVD)形成的二氧化硅和/或氮化硅的一个或多个层。
参考图2C，轻掺杂漏极(LDD)掩模198在衬底102上并且可选地在n型阱122中形成，其使邻近浮栅130、栅极150和栅极164的区域暴露。N型掺杂剂200(例如磷和可能的砷)被植入由LDD掩模198暴露的衬底102中(例如在30keV至70keV的能量下以2×1013cm-2至1×1014cm-2的总剂量)，以形成邻近浮栅130、栅极150和栅极164的漏极扩展植入区202和n型阱122中的阱抽头植入区204。浮栅130、栅极150和栅极164阻挡n型掺杂剂200。例如参考图2A所描述，随后移除LDD掩模198。
参考图2D，在衬底102的上方形成深源极/漏极掩模206，其使存取晶体管110和逻辑NMOS晶体管112以及n型阱122暴露，并且可以可选地使图2D中描绘的感测晶体管108暴露。将N型掺杂剂208(例如磷和砷)植入到邻近浮栅130、栅极150和栅极164的衬底102中并且植入在n型阱122中(例如在40keV至70keV的能量下以1×1015cm-2至5×1015cm-2的总剂量)，以形成邻近浮栅130、栅极150和栅极164的深源极/漏极植入区210，并且形成在n型阱122中的接触植入区212。浮栅130、栅极150和栅极164阻挡n型掺杂剂208。例如参考图2A所描述，随后移除深源极/漏极掩模206。
参考图2E，衬底102被退火以激活在漏极延伸植入区202、阱抽头植入区204、深源极/漏极植入区210和图2D的接触植入区212中的植入的掺杂剂，以形成感测源极/漏极区138的深源极/漏极部分142、形成存取源极/漏极区152的深源极/漏极部分154、形成逻辑源极/漏极区166的深源极/漏极部分168，并且形成n型阱122中的接触区160。衬底102可以例如通过在快速热处理(RTP)工具中的尖峰退火工艺、或通过闪速退火工艺、或通过激光退火工艺来退火。
硅化物阻挡(block)介电材料层214在集成电路100的现存顶表面的上方形成。例如，硅化物阻挡介电材料层214可以包含二氧化硅和可能的氮化硅的一个或多个子层，其中总厚度为10纳米到50纳米。在硅化物阻挡介电材料层214中的二氧化硅由PECVD工艺形成。
参考图2F，图2E的硅化物阻挡介电材料层214被图案化以覆盖感测晶体管108的浮栅130以便形成图1的顶部栅极介电层134的第一部分，并且使感测源极/漏极区138的深源极/漏极部分142、存取源极/漏极区152的深源极/漏极部分154、逻辑源极/漏极区166的深源极/漏极部分168，以及n型阱122中的接触区160、存取晶体管110的栅极150和逻辑NMOS晶体管112的栅极164暴露。可以通过由光刻工艺形成蚀刻掩模并且由湿法蚀刻工艺或RIE工艺移除被蚀刻掩模暴露的硅化物阻挡介电材料层214来使硅化物阻挡介电材料层214图案化。
在由图案化的硅化物阻挡介电材料层214暴露的硅上形成金属硅化物174。例如，可以通过在暴露的硅上形成难熔金属(例如钛、钴或镍)层并且加热衬底102以使暴露的硅与难熔金属反应以形成金属硅化物174来形成金属硅化物174。随后通过湿法蚀刻工艺(例如硫酸和过氧化氢的含水混合物，或氢氧化铵和过氧化氢的含水混合物)移除未反应的金属。
参考图2G，介电势垒层216在金属硅化物174的上方形成并且部分地形成图1中的顶部栅极介电层134。介电势垒层216可以是包含5纳米至20纳米厚的二氧化硅的第一子层、在二氧化硅的第一子层上的5纳米至20纳米厚的氮化硅的子层、以及在氮化硅的子层上的5纳米至20纳米厚的二氧化硅的第二子层的层堆叠。可以使用四乙氧基硅烷(TEOS)通过PECVD形成介电势垒层216中的二氧化硅。可以使用双叔丁基氨基硅烷(BTBAS)通过PECVD形成介电势垒层216中的氮化硅。用于介电势垒层216的其它层结构或组分在该示例的范围内。例如，介电势垒层216的总厚度可以是20纳米到40纳米。
栅极金属层218在介电势垒层216上形成。例如，栅极金属层218可以是40纳米至80纳米厚并且可以包含氮化钽、钽、氮化钛或钛。栅极金属层218中的钛和钽可以通过溅射形成。栅极金属层218中的氮化钽和氮化钛可以通过氮环境中或原子层沉积中的反应溅射来形成。
硬掩模层220在栅极金属层218上形成。硬掩模层220可以包含通过PECVD形成的氮化硅并且可以是25纳米至50纳米厚。
栅极掩模222在硬掩模层220的上方形成，栅极掩模222覆盖用于图1的金属感测栅极136的区域。栅极掩模222在其它处使硬掩模层220暴露，包括在感测晶体管108的深源极/漏极部分142的上方和在存取晶体管110和逻辑NMOS晶体管112的上方。栅极掩模222可以通过光刻工艺由光刻胶形成。栅极掩模222的宽度被选择以提供允许在栅极金属层218的湿法蚀刻期间用于底切的金属感测栅极136的期望宽度。如参考图1所讨论的，形成具有至少400纳米的宽度的浮栅130有利地使栅极掩模222能够被形成有充足的宽度以提供金属感测栅极136的期望宽度。
参考图2H，在图2G中被栅极掩模222暴露的硬掩模层220通过RIE工艺被移除，留下在栅极掩模222下方的硬掩模层220以形成硬掩模224。栅极掩模222可以在随后的金属栅极蚀刻工艺中被移除或保留在适当位置。
参考图2I，在图2H中被硬掩模224暴露的栅极金属层218被移除，留下在硬掩模224下方的栅极金属层218以提供金属感测栅极136。可以利用浓氢氧化铵和过氧化氢的水混合物通过湿法蚀刻移除栅极金属层218。蚀刻栅极金属层218的其他方法在该示例的范围内。如在图2I中所描绘，图2H的栅极掩模222可以通过湿法蚀刻工艺侵蚀，或可以被完全移除。湿法蚀刻工艺可以底切栅极金属层218。介电势垒层216在栅极金属层218的移除期间保护金属硅化物174。硬掩模224可以在介电势垒层216在适当位置时被移除，或者在随后的制造步骤期间被移除。
参考图2J，图2I中被金属感测栅极136暴露的介电势垒层216被移除。介电势垒层216可以通过对金属硅化物174有选择性的等离子体蚀刻工艺来移除。介电势垒层216保留在金属感测栅极136的下方以提供顶部栅极介电层134的第二部分。图案化的硅化物阻挡介电材料层214和介电势垒层216的组合提供顶部栅极介电层134。
硬掩模224(如果保留的话)被移除。集成电路100的制造继续形成图1的PMD层176。因此利用一个额外的光刻操作(图2G的栅极掩模222)形成闪速存储器106，与具有需要三个额外的光刻操作的常规嵌入式闪速存储器的等效集成电路相比，有利地降低了集成电路100的成本。
在所描述的实施例中修改是可能的，并且在权利要求的范围内其它实施例是可能的。

Claims (20)

1.一种包含闪速存储器的集成电路，其包括：
包含半导体材料的衬底；
所述闪速存储器的感测晶体管，其包括：
设置在所述衬底的顶表面处的栅极介电层；
设置在所述栅极介电层上的宽度为至少400纳米的多晶硅的浮栅；
设置在所述衬底中的在所述浮栅的下方部分地延伸的第一源极/漏极区和第二源极/漏极区，所述第一源极/漏极区和所述第二源极/漏极区被隔开小于200纳米；
设置在所述浮栅上方的顶部栅极介电层；以及
设置在所述顶部栅极介电层上的金属感测栅极。
2.根据权利要求1所述的集成电路，其中所述金属感测栅极包含选自包括钽、氮化钽、钛和氮化钛的组中的金属。
3.根据权利要求1所述的集成电路，其中所述顶部栅极介电层是包含二氧化硅的子层和氮化硅的子层的层堆叠。
4.根据权利要求1所述的集成电路，其中所述顶部栅极介电层跨越所述浮栅的所述宽度延伸。
5.根据权利要求1所述的集成电路，其中所述感测晶体管的所述第一源极/漏极区和所述第二源极/漏极区包含设置在所述浮栅外侧的深源极/漏极部分。
6.根据权利要求5所述的集成电路，其包括在所述第一源极/漏极区和所述第二源极/漏极区的所述深源极/漏极部分上方的所述衬底的所述顶表面处的金属硅化物。
7.根据权利要求1所述的集成电路，其中所述金属感测栅极的厚度为40纳米至80纳米。
8.根据权利要求1所述的集成电路，其包括具有铜镶嵌结构的金属互连件，所述铜镶嵌结构包括与所述金属感测栅极相同的金属的沟槽衬垫。
9.根据权利要求1所述的集成电路，其包括具有栅极介电层的逻辑n沟道金属氧化物半导体晶体管即NMOS晶体管，所述栅极介电层具有与所述感测晶体管的所述栅极介电层相同的厚度。
10.一种形成包含闪速存储器的集成电路的方法，其包括下列步骤：
提供包括半导体材料的衬底；
在所述衬底的顶表面的上方形成感测源极/漏极掩模，所述感测源极/漏极掩模使用于所述闪速存储器的感测晶体管的第一感测源极/漏极区和第二感测源极/漏极区的区域中的衬底暴露并且覆盖在用于所述第一感测源极/漏极区和所述第二感测源极/漏极区的所述区域之间的所述衬底；
将掺杂剂植入到由所述感测源极/漏极掩模暴露的所述区域中的所述衬底中；
移除所述感测源极/漏极掩模；
在移除所述感测源极/漏极掩模之后，在所述衬底的所述顶表面上形成所述感测晶体管的栅极介电层；
在所述栅极介电层上形成宽度至少为400纳米的多晶硅的浮栅；
激活所植入的掺杂剂以形成在所述浮栅下方部分地延伸的第一感测源极/漏极区和第二感测源极/漏极区，所述第一感测源极/漏极区和所述第二感测源极/漏极区被隔开小于200纳米；
在所述浮栅的上方形成顶部栅极介电层；
在所述顶部栅极介电层的上方形成栅极金属层；
在所述栅极金属层的上方形成掩模，使得所述掩模覆盖在所述浮栅上方的用于金属感测栅极的区域；以及
移除被所述掩模暴露的所述栅极金属层以在所述顶部栅极介电层上形成所述金属感测栅极。
11.根据权利要求10所述的方法，其中所述金属感测栅极包含选自包括钽、氮化钽、钛和氮化钛的组中的金属。
12.根据权利要求10所述的方法，其包括使用所述浮栅作为掩模将掺杂剂植入到邻近所述浮栅的所述衬底中，以形成所述第一感测源极/漏极区和所述第二感测源极/漏极区的深源极/漏极部分，所述深源极/漏极部分被设置在所述浮栅的外侧。
13.根据权利要求12所述的方法，其包括在所述第一感测源极/漏极区和所述第二感测源极/漏极区的所述深源极/漏极部分上形成金属硅化物。
14.根据权利要求13所述的方法，其包括下列步骤：
在所述浮栅和所述第一感测源极/漏极区和所述第二感测源极/漏极区的所述深源极/漏极部分的上方形成硅化物阻挡介电材料层；
在形成所述金属硅化物之前，将所述硅化物阻挡介电材料层图案化以留下在所述浮栅上方的所述硅化物阻挡材料层并且移除在所述第一感测源极/漏极区和所述第二感测源极/漏极区的所述深源极/漏极部分的上方的所述硅化物阻挡介电材料层；
在形成所述栅极金属层之前，在所述浮栅上的所述硅化物阻挡介电材料层的上方和在所述金属硅化物的上方形成介电势垒层；以及
在移除所述栅极金属层之后从所述金属硅化物的上方移除所述介电势垒层以形成所述金属感测栅极，其中所述硅化物阻挡介电材料层和所述介电势垒层的组合提供所述顶部栅极介电层。
15.根据权利要求14所述的方法，其中所述硅化物阻挡介电材料层包含二氧化硅，并且所述介电势垒层是包含二氧化硅的子层和氮化硅的子层的层堆叠。
16.根据权利要求10所述的方法，其包括下列步骤：
在介电层中形成互连沟槽；
在所述互连沟槽的侧壁和底部上形成沟槽衬垫；以及
在所述沟槽衬垫上形成铜，其中所述沟槽衬垫具有与所述金属感测栅极相同的组分。
17.根据权利要求10所述的方法，其中移除被所述掩模暴露的所述栅极金属层以形成所述金属感测栅极通过湿法蚀刻工艺来执行。
18.根据权利要求17所述的方法，其中所述湿法蚀刻工艺包括浓氢氧化铵和过氧化氢的水溶液。
19.根据权利要求10所述的方法，其包括同时形成逻辑NMOS晶体管的栅极介电层和所述感测晶体管的所述栅极介电层。
20.一种形成包含闪速存储器的集成电路的方法，其包括步骤：
提供包含半导体材料的衬底；
在所述衬底的顶表面的上方形成感测源极/漏极掩模，所述感测源极/漏极掩模使用于所述闪速存储器的感测晶体管的感测源极漏极区的区域中的衬底暴露并且覆盖在用于所述感测源极漏极区的所述区域之间的所述衬底；
将掺杂剂植入到由所述感测源极/漏极掩模暴露的所述区域中的所述衬底中；
移除所述感测源极/漏极掩模；
在移除所述感测源极/漏极掩模之后，在所述衬底的所述顶表面上形成所述感测晶体管的栅极介电层；
在所述栅极介电层上形成所述感测晶体管的宽度至少为400纳米的多晶硅的浮栅；
激活所植入的掺杂剂以形成所述感测晶体管的在所述浮栅下方部分地延伸的感测源极/漏极区，所述感测源极/漏极区被隔开小于200纳米；
使用所述浮栅作为掩模将掺杂剂植入邻近所述浮栅的所述衬底中，以形成所述感测源极/漏极区的深源极/漏极部分，所述深源极/漏极部分被设置在所述浮栅的外侧；
在所述浮栅和所述感测源极/漏极区的所述深源极/漏极部分的上方形成硅化物阻挡介电材料层；
将所述硅化物阻挡介电材料层图案化以留下在所述浮栅上方的所述硅化物阻挡材料层并且移除在所述感测源极/漏极区的所述深源极/漏极部分的上方的所述硅化物阻挡介电材料层；
在所述感测源极/漏极区的所述深源极/漏极部分上形成难熔金属层并且加热所述衬底以在所述深源极/漏极部分上形成金属硅化物，其中在所述浮栅上的图案化的硅化物阻挡介电材料层防止在所述栅极上形成金属硅化物，并且随后移除未反应的金属；
在所述浮栅上的所述图案化的硅化物阻挡介电材料层的上方和在所述金属硅化物的上方形成介电势垒层；
在所述介电势垒层的上方形成栅极金属层；
在所述栅极金属层的上方形成硬掩模层；
移除所述金属硅化物上方的所述硬掩模层以在所述浮栅上方形成硬掩模；
移除被所述硬掩模暴露的所述栅极金属层以在所述浮栅上方形成所述感测晶体管的金属感测栅极；以及
在形成所述金属感测栅极之后，从所述金属硅化物上方移除所述介电势垒层，其中所述硅化物阻挡介电材料层和所述介电势垒层的组合提供所述感测晶体管的顶部栅极介电层。
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