JP7010687B2 - 半導体装置の製造方法および半導体装置 - Google Patents
半導体装置の製造方法および半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims description 199
- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 239000000758 substrate Substances 0.000 claims description 136
- 238000000034 method Methods 0.000 claims description 92
- 238000012216 screening Methods 0.000 claims description 73
- 230000008569 process Effects 0.000 claims description 47
- 230000002950 deficient Effects 0.000 claims description 35
- 238000000059 patterning Methods 0.000 claims description 18
- 230000005684 electric field Effects 0.000 claims description 16
- 239000000523 sample Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 7
- 229920006395 saturated elastomer Polymers 0.000 claims description 7
- 230000002093 peripheral effect Effects 0.000 claims description 5
- 239000012528 membrane Substances 0.000 claims 2
- 239000010408 film Substances 0.000 description 346
- 230000007547 defect Effects 0.000 description 68
- 235000012431 wafers Nutrition 0.000 description 57
- 238000011109 contamination Methods 0.000 description 23
- 239000010410 layer Substances 0.000 description 16
- 238000012360 testing method Methods 0.000 description 14
- 230000005856 abnormality Effects 0.000 description 13
- 238000009792 diffusion process Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 238000000926 separation method Methods 0.000 description 10
- 239000000126 substance Substances 0.000 description 10
- 230000000694 effects Effects 0.000 description 9
- 230000015572 biosynthetic process Effects 0.000 description 8
- 230000006378 damage Effects 0.000 description 8
- 238000009413 insulation Methods 0.000 description 8
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 6
- 239000002356 single layer Substances 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 239000002245 particle Substances 0.000 description 5
- 239000010409 thin film Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000006872 improvement Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000002159 abnormal effect Effects 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 229910001873 dinitrogen Inorganic materials 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 229910052757 nitrogen Inorganic materials 0.000 description 3
- 239000003870 refractory metal Substances 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000002484 cyclic voltammetry Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 230000003111 delayed effect Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011259 mixed solution Substances 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000000275 quality assurance Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000001172 regenerating effect Effects 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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Description
(1)ウェハプロセスが終了した個別半導体装置毎にスクリーニングを行うので、半導体装置の電気特性試験時間が長くなってしまう。
ウェハ形状の半導体基板上にゲート絶縁膜とゲート電極膜を有する半導体装置の製造方法であって、
前記ウェハ形状の半導体基板上にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜を含む前記ウェハ形状の半導体基板の全面にゲート電極膜を形成する工程と、
前記ゲート電極膜を形成する工程の後に、前記ウェハ形状の半導体基板の全面に形成されている前記ゲート電極膜と前記ウェハ形状の半導体基板の裏面との間に電位差を設け、前記ゲート絶縁膜に電界を印加することで前記ゲート絶縁膜をスクリーニングする工程と、
前記スクリーニングを施した前記ウェハ形状の半導体基板を判定する工程と、
前記判定する工程の後に、前記ゲート電極膜をパターニングする工程と、
を備えることを特徴とする半導体装置の製造方法とした。
(1)ウェハ単位でスクリーニングを行うのでチップあたりの実効スクリーニングテスト時間が短い。
図1は本発明の第一の実施形態に係る半導体装置の製造方法を示す工程フロー図である。半導体基板上に半導体装置の要素となるMISトランジスタやMIS容量素子を製造するにあたり、MISトランジスタやMIS容量を構成するゲート絶縁膜形成の前に必要な半導体装置の構造を公知の技術によって作り込んでおく。
スクリーニング時間は、前述の通りスクリーニング対象部にその膜厚に対する真性絶縁耐圧以上の電圧が印加されれば基本的には瞬時破壊に至るため長時間印加する必要はないが、スクリーニング対象薄膜部の膜厚や膜質劣化程度が半導体基板面内で異なることで、ある特定のスクリーニング電圧では破壊に至る時間が異なる事が考えられるため、例えば0.5msec~20sec程度印加すれば良い。
引き続き、MISトランジスタやMIS容量など必要な素子を構成するソース・ドレイン、層間膜、配線や保護膜などを公知の技術で形成し半導体装置を完成させる(工程I)。
工程Kから工程Lは、前述した第一の実施形態の図1の工程Aから工程Bと同様なので説明は省く。
さらに、本発明の第二の実施形態に係る第一のゲート絶縁膜のスクリーニングにおける半導体基板1への電圧印加端子の取り方については第一の実施の形態で図2を用いて説明したものを、スクリーニングの判定については図3を用いて説明したものがそのまま適用できる。
この第二のゲート絶縁膜8形成工程においても、例えば下地となる半導体基板表面にCOP(Crystal Originated Particle)欠陥や異物が存在すると、COP欠陥や異物付着箇所における第二のゲート絶縁膜形成が阻害され、潜在不良の要因となる局所的に所望の第二のゲート絶縁膜厚より薄い膜が形成されてしまう。
本発明の実施形態に係るウェハ端部の第二のゲート電極膜の除去については第一の実施の形態で図4を使って説明したものがそのまま適用できる。
さらに、本発明の第二の実施形態に係るスクリーニングの判定については図3を用いて説明したものがそのまま適用できる。
2 素子分離領域
3、8 ゲート絶縁膜
4、9 ゲート電極膜
5 プローバーの金属製チャック
6 プローブ
7 エッチング液
8 窒素吹出しノズル
21 第一の素子領域
22 第二の素子領域
S1 ゲート電極膜除去幅
S2 ゲート絶縁膜除去幅
Claims (2)
- ウェハ形状の半導体基板上にゲート絶縁膜とゲート電極膜を有する半導体装置の製造方法であって、
前記ウェハ形状の半導体基板の全面にゲート絶縁膜を形成する工程と、
前記ゲート絶縁膜の全面にゲート電極膜を形成する工程と、
前記ウェハ形状の半導体基板の裏面、端面及び表面周辺部に形成された、前記ゲート電極膜及び前記ゲート絶縁膜の両方を除去する工程と、
前記除去する工程の後に、前記ウェハ形状の半導体基板の表面に形成されている前記ゲート電極膜と前記ウェハ形状の半導体基板の裏面との間に電位差を設け、前記ゲート絶縁膜に電界を印加することで前記ゲート絶縁膜をスクリーニングする工程と、
前記スクリーニングを施した前記ウェハ形状の半導体基板を判定する工程と、
前記判定する工程の後に、前記ゲート電極膜をパターニングする工程と、
を備え、
前記ゲート電極膜をスクリーニングする工程は、前記ゲート電極膜に複数のプローブを接続させて行われ、
前記除去する工程は、前記ウェハ形状の半導体基板を回転させつつ前記裏面側からエッチング液を供給し、前記裏面から前記端面及び前記表面周辺部に前記エッチング液を回り込ませることで行われ、前記ウェハ形状の半導体基板の端面から前記ゲート絶縁膜の端面までのゲート絶縁膜除去幅を前記ウェハ形状の半導体基板の端面から前記ゲート電極膜の端面までのゲート電極膜除去幅より小さくすることを特徴とする半導体装置の製造方法。 - 前記判定する工程は、前記電界の印加時間に対する前記半導体基板と前記ゲート電極の間に流れる電流が所定の印加時間までに飽和する場合を良ウェハと判定し、飽和しない非飽和の場合を不良ウェハと判定することを特徴とする請求項1に記載の半導体装置の製造方法。
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TW107104968A TW201838038A (zh) | 2017-02-17 | 2018-02-12 | 半導體裝置的製造方法以及半導體裝置 |
KR1020180018196A KR20180095462A (ko) | 2017-02-17 | 2018-02-14 | 반도체 장치의 제조 방법 및 반도체 장치 |
US15/896,356 US10580708B2 (en) | 2017-02-17 | 2018-02-14 | Method of manufacturing a semiconductor device and semiconductor device |
CN201810153387.2A CN108461401A (zh) | 2017-02-17 | 2018-02-22 | 半导体装置的制造方法以及半导体装置 |
US16/743,959 US11043434B2 (en) | 2017-02-17 | 2020-01-15 | Method of manufacturing a semiconductor device |
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CN114089150A (zh) * | 2020-07-03 | 2022-02-25 | 富士电机株式会社 | 半导体芯片的试验装置及试验方法 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000106334A (ja) | 1998-09-28 | 2000-04-11 | Toshiba Corp | 半導体装置の製造方法 |
JP2005085788A (ja) | 2003-09-04 | 2005-03-31 | Oki Electric Ind Co Ltd | 半導体装置のスクリーニング方法 |
JP2005303037A (ja) | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JP2008252009A (ja) | 2007-03-30 | 2008-10-16 | Philtech Inc | 300mmシリコンテストウエハおよび半導体製造装置 |
JP2013120875A (ja) | 2011-12-08 | 2013-06-17 | Renesas Electronics Corp | 半導体ウエハのテスト方法 |
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KR960007478B1 (ko) | 1990-12-27 | 1996-06-03 | 가부시키가이샤 도시바 | 반도체장치 및 반도체장치의 제조방법 |
JPH0992698A (ja) * | 1995-09-26 | 1997-04-04 | Hitachi Ltd | スクリーニング方法および半導体装置 |
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000106334A (ja) | 1998-09-28 | 2000-04-11 | Toshiba Corp | 半導体装置の製造方法 |
JP2005085788A (ja) | 2003-09-04 | 2005-03-31 | Oki Electric Ind Co Ltd | 半導体装置のスクリーニング方法 |
JP2005303037A (ja) | 2004-04-13 | 2005-10-27 | Ricoh Co Ltd | 半導体装置及びその製造方法 |
JP2008252009A (ja) | 2007-03-30 | 2008-10-16 | Philtech Inc | 300mmシリコンテストウエハおよび半導体製造装置 |
JP2013120875A (ja) | 2011-12-08 | 2013-06-17 | Renesas Electronics Corp | 半導体ウエハのテスト方法 |
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