JP6808641B2 - パルスベースのマルチワイヤリンクのためのクロックおよびデータ復元 - Google Patents

パルスベースのマルチワイヤリンクのためのクロックおよびデータ復元 Download PDF

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Publication number
JP6808641B2
JP6808641B2 JP2017553088A JP2017553088A JP6808641B2 JP 6808641 B2 JP6808641 B2 JP 6808641B2 JP 2017553088 A JP2017553088 A JP 2017553088A JP 2017553088 A JP2017553088 A JP 2017553088A JP 6808641 B2 JP6808641 B2 JP 6808641B2
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Prior art keywords
pulse
signal
wire
clock
interface
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Japanese (ja)
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JP2018516490A5 (enExample
JP2018516490A (ja
Inventor
祥一郎 仙石
祥一郎 仙石
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2017553088A 2015-04-13 2016-03-30 パルスベースのマルチワイヤリンクのためのクロックおよびデータ復元 Expired - Fee Related JP6808641B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562146801P 2015-04-13 2015-04-13
US62/146,801 2015-04-13
US15/084,171 US9621332B2 (en) 2015-04-13 2016-03-29 Clock and data recovery for pulse based multi-wire link
US15/084,171 2016-03-29
PCT/US2016/025094 WO2016167973A1 (en) 2015-04-13 2016-03-30 Clock and data recovery for pulse based multi-wire link

Publications (3)

Publication Number Publication Date
JP2018516490A JP2018516490A (ja) 2018-06-21
JP2018516490A5 JP2018516490A5 (enExample) 2019-04-25
JP6808641B2 true JP6808641B2 (ja) 2021-01-06

Family

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JP2017553088A Expired - Fee Related JP6808641B2 (ja) 2015-04-13 2016-03-30 パルスベースのマルチワイヤリンクのためのクロックおよびデータ復元

Country Status (6)

Country Link
US (3) US9621332B2 (enExample)
EP (1) EP3284229B1 (enExample)
JP (1) JP6808641B2 (enExample)
KR (1) KR20170137735A (enExample)
CN (2) CN111371542B (enExample)
WO (1) WO2016167973A1 (enExample)

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US11251706B2 (en) * 2019-05-15 2022-02-15 Texas Instruments Incorporated Multiphase switched mode power supply clocking circuits and related methods
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KR102817517B1 (ko) * 2020-04-20 2025-06-10 주식회사 엘엑스세미콘 데이터구동장치 및 이의 구동 방법

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Also Published As

Publication number Publication date
CN111371542B (zh) 2022-11-18
KR20170137735A (ko) 2017-12-13
CN111371542A (zh) 2020-07-03
US20170201370A1 (en) 2017-07-13
WO2016167973A1 (en) 2016-10-20
EP3284229A1 (en) 2018-02-21
CN107534548B (zh) 2020-07-31
US9621332B2 (en) 2017-04-11
US20160301519A1 (en) 2016-10-13
US20190149314A1 (en) 2019-05-16
JP2018516490A (ja) 2018-06-21
US10484164B2 (en) 2019-11-19
CN107534548A (zh) 2018-01-02
EP3284229B1 (en) 2021-06-30
US10218492B2 (en) 2019-02-26

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