CN111371542B - 用于基于脉冲的多线链路的时钟和数据恢复的方法和装置 - Google Patents

用于基于脉冲的多线链路的时钟和数据恢复的方法和装置 Download PDF

Info

Publication number
CN111371542B
CN111371542B CN202010112346.6A CN202010112346A CN111371542B CN 111371542 B CN111371542 B CN 111371542B CN 202010112346 A CN202010112346 A CN 202010112346A CN 111371542 B CN111371542 B CN 111371542B
Authority
CN
China
Prior art keywords
connectors
signal
pulse
interface
pulses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010112346.6A
Other languages
English (en)
Chinese (zh)
Other versions
CN111371542A (zh
Inventor
S·森戈库
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of CN111371542A publication Critical patent/CN111371542A/zh
Application granted granted Critical
Publication of CN111371542B publication Critical patent/CN111371542B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
    • H03K5/1534—Transition or edge detectors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0033—Correction by delay
    • H04L7/0037—Delay of clock signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0016—Arrangements for synchronising receiver with transmitter correction of synchronization errors
    • H04L7/0045—Correction by a latch cascade
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0087—Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Theoretical Computer Science (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dc Digital Transmission (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
CN202010112346.6A 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复的方法和装置 Active CN111371542B (zh)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
US201562146801P 2015-04-13 2015-04-13
US62/146,801 2015-04-13
US15/084,171 US9621332B2 (en) 2015-04-13 2016-03-29 Clock and data recovery for pulse based multi-wire link
US15/084,171 2016-03-29
CN201680021338.2A CN107534548B (zh) 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复
PCT/US2016/025094 WO2016167973A1 (en) 2015-04-13 2016-03-30 Clock and data recovery for pulse based multi-wire link

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
CN201680021338.2A Division CN107534548B (zh) 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复

Publications (2)

Publication Number Publication Date
CN111371542A CN111371542A (zh) 2020-07-03
CN111371542B true CN111371542B (zh) 2022-11-18

Family

ID=57111958

Family Applications (2)

Application Number Title Priority Date Filing Date
CN202010112346.6A Active CN111371542B (zh) 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复的方法和装置
CN201680021338.2A Active CN107534548B (zh) 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN201680021338.2A Active CN107534548B (zh) 2015-04-13 2016-03-30 用于基于脉冲的多线链路的时钟和数据恢复

Country Status (6)

Country Link
US (3) US9621332B2 (enExample)
EP (1) EP3284229B1 (enExample)
JP (1) JP6808641B2 (enExample)
KR (1) KR20170137735A (enExample)
CN (2) CN111371542B (enExample)
WO (1) WO2016167973A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9621332B2 (en) 2015-04-13 2017-04-11 Qualcomm Incorporated Clock and data recovery for pulse based multi-wire link
KR20170005330A (ko) * 2015-07-03 2017-01-12 에스케이하이닉스 주식회사 클럭 생성 회로 및 방법, 이를 이용한 반도체 장치 및 전자 시스템
TW201830940A (zh) * 2017-02-08 2018-08-16 陳淑玲 三線式傳輸的穿戴裝置
US10219073B1 (en) * 2017-11-20 2019-02-26 Ford Global Technologies, Llc Vehicle audio system
US10790997B2 (en) 2019-01-23 2020-09-29 Cisco Technology, Inc. Transmission of pulse power and data in a communications network
US11061456B2 (en) 2019-01-23 2021-07-13 Cisco Technology, Inc. Transmission of pulse power and data over a wire pair
US11251706B2 (en) * 2019-05-15 2022-02-15 Texas Instruments Incorporated Multiphase switched mode power supply clocking circuits and related methods
KR20210088808A (ko) 2020-01-06 2021-07-15 삼성전자주식회사 전자 장치 및 전자 장치의 동작 방법
KR102817517B1 (ko) * 2020-04-20 2025-06-10 주식회사 엘엑스세미콘 데이터구동장치 및 이의 구동 방법

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE674358A (enExample) * 1964-12-29 1966-04-15
EP0145188A2 (en) * 1983-10-27 1985-06-19 Westinghouse Electric Corporation Pulsed multichannel protection system with saturable core magnetic logic units
WO2002049314A2 (en) * 2000-12-15 2002-06-20 Qualcomm Incorporated Generating and implementing a communication protocol and interface for high data rate signal transfer
WO2003023587A2 (en) * 2001-09-06 2003-03-20 Qualcomm, Incorporated Generating and implementing a communication protocol and interface for high data rate signal transfer
CN1531718A (zh) * 2000-10-31 2004-09-22 单极型同步通信系统
CN1871635A (zh) * 2003-10-22 2006-11-29 皇家飞利浦电子股份有限公司 通过多条传输线传输数据的方法和设备
EP1976140A1 (en) * 2007-03-26 2008-10-01 Nokia Siemens Networks Gmbh & Co. Kg Method and device for reducing transmission power of packet oriented data and communication system comprising such device
CN101421961A (zh) * 2006-04-19 2009-04-29 高通股份有限公司 低等待时间多跳通信的装置和方法
CN101480026A (zh) * 2006-04-26 2009-07-08 高通股份有限公司 与多个外围设备通信的无线设备
US9112550B1 (en) * 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications
CN105393238A (zh) * 2013-07-23 2016-03-09 高通股份有限公司 三相时钟恢复延迟校准
CN105453067A (zh) * 2013-08-08 2016-03-30 高通股份有限公司 N相信号转变对准

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0654016A (ja) * 1992-08-03 1994-02-25 Fujitsu Ltd スキュー補正回路
JP3129903B2 (ja) * 1994-01-19 2001-01-31 東京エレクトロン株式会社 符号化方法
JPH0946378A (ja) * 1995-07-27 1997-02-14 Meidensha Corp シリアル・データ伝送装置の転送データ変調／復調方式
JPH1188442A (ja) * 1997-09-16 1999-03-30 Yokogawa Electric Corp データ通信装置
JP2000307561A (ja) * 1999-04-21 2000-11-02 Hitachi Ltd バスシステム装置
US6835772B2 (en) 2001-01-29 2004-12-28 Ohashi Chemical Industries Ltd. Low-temperature curing, favorable feel coating composition
US7126378B2 (en) * 2003-12-17 2006-10-24 Rambus, Inc. High speed signaling system with adaptive transmit pre-emphasis
US8068485B2 (en) * 2003-05-01 2011-11-29 Genesis Microchip Inc. Multimedia interface
US7308058B2 (en) 2003-10-27 2007-12-11 Rambus Inc. Transparent multi-mode PAM interface
SG126752A1 (en) * 2004-03-05 2006-11-29 Infineon Technologies Ag Protocols for transmission of data, in particular over telephone lines
US8649460B2 (en) 2007-06-05 2014-02-11 Rambus Inc. Techniques for multi-wire encoding with an embedded clock
US7890788B2 (en) 2007-07-09 2011-02-15 John Yin Clock data recovery and synchronization in interconnected devices
US8291207B2 (en) * 2009-05-18 2012-10-16 Stmicroelectronics, Inc. Frequency and symbol locking using signal generated clock frequency and symbol identification
US9401828B2 (en) * 2010-05-20 2016-07-26 Kandou Labs, S.A. Methods and systems for low-power and pin-efficient communications with superposition signaling codes
GB2499699A (en) * 2011-12-14 2013-08-28 Wolfson Ltd Digital data transmission involving the position of and duration of data pulses within transfer periods
US8653868B2 (en) * 2012-06-28 2014-02-18 Intel Corporation Low power data recovery
JP2014053705A (ja) * 2012-09-06 2014-03-20 Canon Inc 信号伝送方法、及び伝送装置
US9363071B2 (en) 2013-03-07 2016-06-07 Qualcomm Incorporated Circuit to recover a clock signal from multiple wire data signals that changes state every state cycle and is immune to data inter-lane skew as well as data state transition glitches
US9374216B2 (en) 2013-03-20 2016-06-21 Qualcomm Incorporated Multi-wire open-drain link with data symbol transition based clocking
US9178690B2 (en) 2013-10-03 2015-11-03 Qualcomm Incorporated N factorial dual data rate clock and data recovery
US9118457B2 (en) 2013-03-15 2015-08-25 Qualcomm Incorporated Multi-wire single-ended push-pull link with data symbol transition based clocking
US9054941B2 (en) 2013-07-18 2015-06-09 Rf Micro Devices, Inc. Clock and data recovery using dual manchester encoded data streams
US9130735B2 (en) 2013-07-22 2015-09-08 Qualcomm Incorporated Multi-phase clock generation method
JP6317474B2 (ja) * 2014-02-02 2018-04-25 カンドウ ラボズ ソシエテ アノニム 制約ｉｓｉ比を用いる低電力チップ間通信の方法および装置
US20150220472A1 (en) 2014-02-05 2015-08-06 Qualcomm Incorporated Increasing throughput on multi-wire and multi-lane interfaces
KR101615813B1 (ko) * 2014-05-30 2016-05-13 엘지디스플레이 주식회사 시분할 구동방식의 터치 센싱 장치
US9621332B2 (en) 2015-04-13 2017-04-11 Qualcomm Incorporated Clock and data recovery for pulse based multi-wire link
US10313068B1 (en) * 2018-04-24 2019-06-04 Qualcomm Incorporated Signal monitoring and measurement for a multi-wire, multi-phase interface

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BE674358A (enExample) * 1964-12-29 1966-04-15
EP0145188A2 (en) * 1983-10-27 1985-06-19 Westinghouse Electric Corporation Pulsed multichannel protection system with saturable core magnetic logic units
CN1531718A (zh) * 2000-10-31 2004-09-22 单极型同步通信系统
WO2002049314A2 (en) * 2000-12-15 2002-06-20 Qualcomm Incorporated Generating and implementing a communication protocol and interface for high data rate signal transfer
WO2003023587A2 (en) * 2001-09-06 2003-03-20 Qualcomm, Incorporated Generating and implementing a communication protocol and interface for high data rate signal transfer
CN1871635A (zh) * 2003-10-22 2006-11-29 皇家飞利浦电子股份有限公司 通过多条传输线传输数据的方法和设备
CN101421961A (zh) * 2006-04-19 2009-04-29 高通股份有限公司 低等待时间多跳通信的装置和方法
CN101480026A (zh) * 2006-04-26 2009-07-08 高通股份有限公司 与多个外围设备通信的无线设备
EP1976140A1 (en) * 2007-03-26 2008-10-01 Nokia Siemens Networks Gmbh & Co. Kg Method and device for reducing transmission power of packet oriented data and communication system comprising such device
CN105393238A (zh) * 2013-07-23 2016-03-09 高通股份有限公司 三相时钟恢复延迟校准
CN105453067A (zh) * 2013-08-08 2016-03-30 高通股份有限公司 N相信号转变对准
US9112550B1 (en) * 2014-06-25 2015-08-18 Kandou Labs, SA Multilevel driver for high speed chip-to-chip communications

Also Published As

Publication number Publication date
KR20170137735A (ko) 2017-12-13
CN111371542A (zh) 2020-07-03
US20170201370A1 (en) 2017-07-13
WO2016167973A1 (en) 2016-10-20
EP3284229A1 (en) 2018-02-21
CN107534548B (zh) 2020-07-31
US9621332B2 (en) 2017-04-11
US20160301519A1 (en) 2016-10-13
US20190149314A1 (en) 2019-05-16
JP6808641B2 (ja) 2021-01-06
JP2018516490A (ja) 2018-06-21
US10484164B2 (en) 2019-11-19
CN107534548A (zh) 2018-01-02
EP3284229B1 (en) 2021-06-30
US10218492B2 (en) 2019-02-26

Similar Documents

Publication Publication Date Title
CN111371542B (zh) 用于基于脉冲的多线链路的时钟和数据恢复的方法和装置
KR101874765B1 (ko) 데이터 심볼 트랜지션 기반 클록킹에 의한 멀티-와이어 싱글 엔드 푸시-풀 링크
CN107852382B (zh) 用于c-phy 3相发射机的基于时间的均衡
US20150220472A1 (en) Increasing throughput on multi-wire and multi-lane interfaces
JP2016538747A (ja) Ｐｈｙの変更を最小限に抑えかつプロトコルを変更せずにｍｉｐｉ ｄ−ｐｈｙリンクレートを向上させるための方法
US9203599B2 (en) Multi-lane N-factorial (N!) and other multi-wire communication systems
US9735948B2 (en) Multi-lane N-factorial (N!) and other multi-wire communication systems
US9426082B2 (en) Low-voltage differential signaling or 2-wire differential link with symbol transition clocking
CN115462039B (zh) C-phy接口中的单位间隔抖动改进
US9490964B2 (en) Symbol transition clocking clock and data recovery to suppress excess clock caused by symbol glitch during stable symbol period
KR102520096B1 (ko) 인코딩된 멀티-레인 n-팩토리얼 및 다른 멀티-와이어 통신 시스템들
WO2023159415A1 (en) Adaptive low-power signaling to enable link signal error recovery without increased link clock rates

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant