JP6770637B2 - 製造方法、及び、光電子デバイスのアレイ - Google Patents
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Description
本願は、2016年9月19日に出願された米国特許仮出願第62/396,253号の利益を主張するものであり、その内容は参照により本明細書に組み込まれる。
Claims (16)
- III−V族半導体基板上に、第1の分布ブラッグ格子(DBR)を画定する層の第1のセットと、前記第1のDBR上に堆積された量子井戸(QW)層と、前記QW層の上に堆積され、第2のDBRを画定する層の第2のセットと、を含む複数のエピタキシャル層を堆積することと、
その上に前記複数のエピタキシャル層が堆積された前記III−V族半導体基板を、スタンプにダイシングすることと、
シリコン基板上に垂直共振器面発光レーザ(VCSELs)のアレイのための制御回路を作製することと、
前記スタンプのそれぞれの前面を前記制御回路に位置合わせして前記シリコン基板のそれぞれの位置において接合することと、
前記それぞれの前面を接合した後に、前記III−V族半導体基板を、前記スタンプのそれぞれの背面から薄くすることと、
前記III−V族半導体基板を薄くした後に、前記エピタキシャル層をエッチングして個々のエミッタ領域を画定し、前記エミッタ領域を処理してVCSELsを作製することと、
前記VCSELsを作製するためのエミッタ領域のエッチング及び処理をした後に、前記VCSELsを前記制御回路に接続するために、金属トレースを前記VCSELsのそれぞれの背面に亘り堆積させることと、
を含む、製造方法。 - 前記それぞれの前面を接合することは、前記スタンプの前記前面と前記シリコン基板との間にポリマー接着剤を塗布することを含む、請求項1に記載の方法。
- 前記複数のエピタキシャル層を堆積することは、前記エピタキシャル層の前記前面に亘り金属層を堆積させることを含み、前記金属層は、前記VCSELsの前記前面と前記制御回路との間の第1のコンタクトとして使用され、前記金属トレースは、前記制御回路と前記VCSELsの前記背面との間の第2のコンタクトとして使用される、請求項1に記載の方法。
- 前記複数のエピタキシャル層を堆積することは、前記エピタキシャル層の前記前面に亘り金属層を堆積させることを含み、前記それぞれの前面を接合することは、前記スタンプの前記前面における前記金属層を、前記シリコン基板上に堆積された別の金属層に、金属−金属接合で接合することを含む、請求項1に記載の方法。
- 前記それぞれの前面を接合することは、前記スタンプの前記前面と前記シリコン基板との間に酸化物接合部を形成することを含む、請求項1に記載の方法。
- 前記金属トレースを堆積させることは、個々のコンタクトを前記VCSELsに取り付けて、前記VCSELsのそれぞれを前記制御回路によって個別に制御できるようにすることを含む、請求項1から5のいずれか一項に記載の方法。
- 前記金属トレースを堆積させることは、それぞれの共有コンタクトを前記VCSELsの事前に定義されたグループに取り付けて、前記グループそれぞれを前記制御回路によって一括制御できるようにすることを含む、請求項1から5のいずれか一項に記載の方法。
- 前記堆積された金属トレースの少なくとも一部は、前記VCSELsの前記背面と前記シリコン基板上の前記制御回路との間に延在する、請求項1から5のいずれか一項に記載の方法。
- 前記金属トレースを堆積させた後に、前記シリコン基板をダイシングして、前記VCSELsのうちの1つ以上と、前記VCSELsのうちの前記1つ以上に接続されている前記制御回路とをそれぞれが含む複数のチップを形成することを含む、請求項1から5のいずれか一項に記載の方法。
- 前記シリコン基板上に光検出器を、前記VCSELsの前記それぞれの前面を前記シリコン基板に接合した後に前記光検出器が前記チップ上の前記VCSELsに沿って配置されるように選択された位置に作製することを含む、請求項9に記載の方法。
- 前記光検出器を作製することは、前記光検出器を前記シリコン基板上にマトリクス状のジオメトリで配置することと、各チップから画像データを出力するように、前記光検出器に接続された読み出し回路を前記シリコン基板上に形成することと、を含む、請求項10に記載の方法。
- 前記VCSELsの前記背面にマイクロレンズを形成することを含む、請求項1から5のいずれか一項に記載の方法。
- シリコン基板と、
前記シリコン基板上に作製された垂直共振器面発光レーザ(VCSELs)のアレイのための制御回路と、
第1の分布ブラッグ格子(DBR)を画定する層の第1のセットと、前記第1のDBR上に堆積された量子井戸(QW)層と、前記QW層の上に堆積され、第2のDBRを画定する層の第2のセットと、を含む複数のエピタキシャル層を含むIII−V族半導体基板からダイシングされた複数のスタンプであって、前記制御回路に位置合わせされて前記シリコン基板のそれぞれの位置に接合されたそれぞれの前面を有しており、前記エピタキシャル層によって画定された個々のエミッタ領域を含み、そのそれぞれの背面を介して放射線を放出するように構成されている前記VCSELsを含む、スタンプと、
前記VCSELsのそれぞれの背面に亘り堆積されており、かつ前記VCSELsを前記制御回路に接続する金属トレースと、
前記VCSELsのそれぞれの前面に亘り堆積されており、前記VCSELsの前記前面と前記制御回路との間の共通コンタクトとして使用される金属層と、を備える、光電子デバイスのアレイ。 - 前記金属トレースは、前記VCSELsとの個々のコンタクトとして構成されていて、前記VCSELsのそれぞれを前記制御回路によって個別に制御できる、請求項13に記載のデバイスのアレイ。
- 前記金属トレースは共有コンタクトとして構成されており、前記共有コンタクトは、前記VCSELsのそれぞれのグループに取り付けられていて、前記グループそれぞれを前記制御回路によって一括制御できる、請求項13に記載のデバイスのアレイ。
- 前記シリコン基板上に作製された光検出器であって、前記スタンプの前記それぞれの前面を前記シリコン基板に接合した後に前記光検出器が前記スタンプに沿って配置されるように選択された位置に作製されている光検出器を備える、請求項13に記載のデバイスのアレイ。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US201662396253P | 2016-09-19 | 2016-09-19 | |
US62/396,253 | 2016-09-19 | ||
PCT/US2017/051948 WO2018053378A1 (en) | 2016-09-19 | 2017-09-18 | Vertical emitters integrated on silicon control backplane |
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JP2020159986A Division JP7165170B2 (ja) | 2016-09-19 | 2020-09-24 | 製造方法、及び、光電子デバイス |
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JP2019530234A (ja) | 2019-10-17 |
EP3497757A1 (en) | 2019-06-19 |
KR20190035899A (ko) | 2019-04-03 |
KR102209661B1 (ko) | 2021-01-28 |
KR20200113008A (ko) | 2020-10-05 |
CN109716600A (zh) | 2019-05-03 |
US20190363520A1 (en) | 2019-11-28 |
JP7165170B2 (ja) | 2022-11-02 |
WO2018053378A1 (en) | 2018-03-22 |
JP2021013027A (ja) | 2021-02-04 |
KR102160549B1 (ko) | 2020-09-28 |
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