JP6740219B2 - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
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- JP6740219B2 JP6740219B2 JP2017517597A JP2017517597A JP6740219B2 JP 6740219 B2 JP6740219 B2 JP 6740219B2 JP 2017517597 A JP2017517597 A JP 2017517597A JP 2017517597 A JP2017517597 A JP 2017517597A JP 6740219 B2 JP6740219 B2 JP 6740219B2
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- 239000004065 semiconductor Substances 0.000 title claims description 78
- 238000009792 diffusion process Methods 0.000 claims description 22
- 239000002184 metal Substances 0.000 claims description 8
- 229910052751 metal Inorganic materials 0.000 claims description 8
- 239000004020 conductor Substances 0.000 description 43
- 230000007257 malfunction Effects 0.000 description 6
- 230000006866 deterioration Effects 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 230000006870 function Effects 0.000 description 3
- 239000000470 constituent Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0064—Verifying circuits or methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/79—Array wherein the access device being a transistor
Description
はじめに本開示の基礎となった知見について説明する。
図2に、第1の実施形態にかかる半導体記憶装置10の断面図を示す。
次に、第2の実施形態について説明する。
次に、第3の実施形態について説明する。
次に、第4の実施形態について説明する。
次に、第5の実施形態について説明する。
次に、第6の実施形態について説明する。
4、4a、4b、4c 導体(配線層)
5、6 リークパス
10、20、30、40、50、60、1000 半導体記憶装置
100、1100 第1の記憶素子
101 第1の上部電極
102 第1の抵抗体
103 第1の下部電極
104、1104 第2の記憶素子
105 第2の上部電極
106 第2の抵抗体
107、107a、1107 第2の下部電極
108、1108 第1の選択線
109、1109 第2の選択線
110 導電層
111a 拡散層
111b 半導体基板
112、113、114 MOSトランジスタ
112a、112b、113a、113b、114a、114b ソース−ドレイン電極
112c、113c、114c ゲート電極
1200 第3の記憶素子
1201 第4の記憶素子
1204 第1のリークパス
1205 第2のリークパス
Claims (12)
- 上部電極と、前記上部電極の下方に配置された下部電極と、前記上部電極と前記下部電極との間に配置された抵抗体とを各々有する複数の記憶素子と、
第1の選択線と、
第2の選択線と、
前記第1の選択線とは異なる配線層に配置され、かつ前記第2の選択線と電気的に分離された導電層と、
を備え、
前記複数の記憶素子のうち第1の記憶素子は、前記上部電極として第1の上部電極、および、前記下部電極として第1の下部電極を有し、
前記第1の上部電極は、前記第1の選択線と接続され、
前記第1の下部電極は、前記第2の選択線と接続され、
前記複数の記憶素子のうち、前記第1の記憶素子に隣接して配置される第2の記憶素子は、前記上部電極として第2の上部電極、および、前記下部電極として第2の下部電極を有し、
前記第2の上部電極は、前記第1の選択線と接続され、
前記第2の下部電極は、前記第2の記憶素子以外の記憶素子の前記抵抗体を介さずに、前記導電層を介して前記第1の選択線と接続されている
半導体記憶装置。 - 前記第1の記憶素子は、高抵抗状態または低抵抗状態を保持することにより記憶を行うメモリセルであり、
前記第2の記憶素子は、記憶を行わないダミーメモリセルであり、
前記ダミーメモリセルは、前記メモリセルの周囲に配置されている
請求項1に記載の半導体記憶装置。 - 前記導電層は、拡散層である
請求項1または2に記載の半導体記憶装置。 - 前記拡散層にはMOSトランジスタが形成され、前記MOSトランジスタを介して、前記第2の下部電極と前記第1の選択線とが接続されている
請求項3に記載の半導体記憶装置。 - 前記導電層は、金属層である
請求項1または2に記載の半導体記憶装置。 - 前記導電層は、金属層および前記金属層に接続された拡散層である
請求項1または2に記載の半導体記憶装置。 - 前記第2の下部電極は、前記第1の記憶素子が配置された側と反対側に延伸した延伸部分を有し、前記延伸部分において前記第2の下部電極に接続された配線層を介して前記第1の選択線と接続されている
請求項1または2に記載の半導体記憶装置。 - 前記半導体記憶装置は、さらに、
前記第2の記憶素子に隣接しかつ前記第1の記憶素子が配置された側と反対側に第3の記憶素子を備え、
前記第2の記憶素子の前記第2の下部電極は、前記第3の記憶素子が有する第3の下部電極を介して、縦方向の配線層と接続されている
請求項1または2に記載の半導体記憶装置。 - 前記第3の記憶素子は、記憶を行わないダミーメモリセルである
請求項8に記載の半導体記憶装置。 - 前記第1の選択線と前記導電層とは、縦方向の配線層により直接接続されている
請求項1または2に記載の半導体記憶装置。 - 前記第2の記憶素子は、前記第1の記憶素子より高抵抗である
請求項1または2に記載の半導体記憶装置。 - 前記第1の記憶素子は、さらに、前記第1の下部電極と前記抵抗体との間にダイオードを有している
請求項1または2に記載の半導体記憶装置。
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JP2015098293 | 2015-05-13 | ||
JP2015098293 | 2015-05-13 | ||
PCT/JP2016/001983 WO2016181609A1 (ja) | 2015-05-13 | 2016-04-12 | 半導体記憶装置 |
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JPWO2016181609A1 JPWO2016181609A1 (ja) | 2018-03-01 |
JP6740219B2 true JP6740219B2 (ja) | 2020-08-12 |
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US (1) | US10573810B2 (ja) |
JP (1) | JP6740219B2 (ja) |
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WO (1) | WO2016181609A1 (ja) |
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JP2011061091A (ja) * | 2009-09-11 | 2011-03-24 | Toshiba Corp | 半導体記憶装置 |
JP2011138581A (ja) * | 2009-12-28 | 2011-07-14 | Toshiba Corp | 半導体記憶装置 |
JP2012054345A (ja) * | 2010-08-31 | 2012-03-15 | Toshiba Corp | 三次元不揮発性半導体メモリ |
CN103548086B (zh) | 2011-07-06 | 2016-08-31 | 松下电器产业株式会社 | 半导体存储装置 |
JP2013089662A (ja) | 2011-10-14 | 2013-05-13 | Renesas Electronics Corp | 半導体装置 |
JP6260832B2 (ja) * | 2012-10-30 | 2018-01-17 | パナソニックIpマネジメント株式会社 | 不揮発性半導体記憶装置 |
KR101952272B1 (ko) * | 2012-11-06 | 2019-02-26 | 삼성전자주식회사 | 반도체 기억 소자 |
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2016
- 2016-04-12 WO PCT/JP2016/001983 patent/WO2016181609A1/ja active Application Filing
- 2016-04-12 JP JP2017517597A patent/JP6740219B2/ja active Active
- 2016-04-12 CN CN201680026965.5A patent/CN107534043B/zh active Active
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2017
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Publication number | Publication date |
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CN107534043B (zh) | 2020-10-27 |
CN107534043A (zh) | 2018-01-02 |
WO2016181609A1 (ja) | 2016-11-17 |
US10573810B2 (en) | 2020-02-25 |
US20180069177A1 (en) | 2018-03-08 |
JPWO2016181609A1 (ja) | 2018-03-01 |
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