JP6626687B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents
配線基板、半導体装置及び配線基板の製造方法 Download PDFInfo
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- JP6626687B2 JP6626687B2 JP2015211723A JP2015211723A JP6626687B2 JP 6626687 B2 JP6626687 B2 JP 6626687B2 JP 2015211723 A JP2015211723 A JP 2015211723A JP 2015211723 A JP2015211723 A JP 2015211723A JP 6626687 B2 JP6626687 B2 JP 6626687B2
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1431—Logic devices
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1432—Central processing unit [CPU]
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
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- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
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| JP2015211723A JP6626687B2 (ja) | 2015-10-28 | 2015-10-28 | 配線基板、半導体装置及び配線基板の製造方法 |
| US15/297,782 US9799595B2 (en) | 2015-10-28 | 2016-10-19 | Careless wiring substrate having an insulation layer with a bulged covering portion and semiconductor device thereof |
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| JP2015211723A JP6626687B2 (ja) | 2015-10-28 | 2015-10-28 | 配線基板、半導体装置及び配線基板の製造方法 |
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| JP7548086B2 (ja) * | 2021-03-19 | 2024-09-10 | 三菱電機株式会社 | 半導体装置の製造方法 |
| TWI803312B (zh) * | 2021-12-23 | 2023-05-21 | 南亞科技股份有限公司 | 具有多堆疊載體結構之半導體元件 |
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| JP4800253B2 (ja) * | 2007-04-04 | 2011-10-26 | 新光電気工業株式会社 | 配線基板の製造方法 |
| JP5003812B2 (ja) * | 2009-12-10 | 2012-08-15 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
| JP5675443B2 (ja) * | 2011-03-04 | 2015-02-25 | 新光電気工業株式会社 | 配線基板及び配線基板の製造方法 |
| US8923008B2 (en) * | 2011-03-08 | 2014-12-30 | Ibiden Co., Ltd. | Circuit board and method for manufacturing circuit board |
| JP6223909B2 (ja) * | 2013-07-11 | 2017-11-01 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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| US9799595B2 (en) | 2017-10-24 |
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