JP6608108B2 - 配線基板、半導体装置及び配線基板の製造方法 - Google Patents

配線基板、半導体装置及び配線基板の製造方法 Download PDF

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Publication number
JP6608108B2
JP6608108B2 JP2015255103A JP2015255103A JP6608108B2 JP 6608108 B2 JP6608108 B2 JP 6608108B2 JP 2015255103 A JP2015255103 A JP 2015255103A JP 2015255103 A JP2015255103 A JP 2015255103A JP 6608108 B2 JP6608108 B2 JP 6608108B2
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Japan
Prior art keywords
layer
wiring
hole
wiring layer
opening
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Active
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JP2015255103A
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English (en)
Japanese (ja)
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JP2017118067A (ja
JP2017118067A5 (https=
Inventor
桂 今藤
恵資 吉澤
裕一 吉野
健太 内山
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2015255103A priority Critical patent/JP6608108B2/ja
Priority to US15/381,916 priority patent/US9899304B2/en
Publication of JP2017118067A publication Critical patent/JP2017118067A/ja
Publication of JP2017118067A5 publication Critical patent/JP2017118067A5/ja
Application granted granted Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/083—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being via holes penetrating underlying conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
JP2015255103A 2015-12-25 2015-12-25 配線基板、半導体装置及び配線基板の製造方法 Active JP6608108B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2015255103A JP6608108B2 (ja) 2015-12-25 2015-12-25 配線基板、半導体装置及び配線基板の製造方法
US15/381,916 US9899304B2 (en) 2015-12-25 2016-12-16 Wiring substrate and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015255103A JP6608108B2 (ja) 2015-12-25 2015-12-25 配線基板、半導体装置及び配線基板の製造方法

Publications (3)

Publication Number Publication Date
JP2017118067A JP2017118067A (ja) 2017-06-29
JP2017118067A5 JP2017118067A5 (https=) 2018-11-22
JP6608108B2 true JP6608108B2 (ja) 2019-11-20

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Family Applications (1)

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JP2015255103A Active JP6608108B2 (ja) 2015-12-25 2015-12-25 配線基板、半導体装置及び配線基板の製造方法

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Country Link
US (1) US9899304B2 (https=)
JP (1) JP6608108B2 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6771308B2 (ja) * 2016-05-02 2020-10-21 三菱電機株式会社 回路基板および半導体集積回路の実装構造
KR20180098009A (ko) * 2017-02-24 2018-09-03 삼성전자주식회사 인쇄회로기판 및 이를 가지는 반도체 패키지
TWI693872B (zh) * 2018-10-29 2020-05-11 欣興電子股份有限公司 電路板製造方法
JP7336258B2 (ja) * 2019-05-15 2023-08-31 イビデン株式会社 プリント配線板およびその製造方法
JP7378247B2 (ja) * 2019-09-05 2023-11-13 イビデン株式会社 プリント配線板およびその製造方法
JP7451971B2 (ja) * 2019-11-29 2024-03-19 大日本印刷株式会社 配線基板
KR102872610B1 (ko) 2020-04-09 2025-10-17 에스케이하이닉스 주식회사 매립된 솔더의 접합 구조를 구비하는 반도체 패키지 및 이의 제조 방법
KR102810485B1 (ko) 2020-04-14 2025-05-21 에스케이하이닉스 주식회사 가변 저항층을 포함하는 반도체 장치
KR102933110B1 (ko) 2021-09-16 2026-03-03 엘지이노텍 주식회사 회로기판 및 이를 포함하는 패키지 기판
US11751334B2 (en) * 2021-10-22 2023-09-05 Nanya Technology Corporation Semiconductor device with interface structure and method for fabricating the same
JP7768061B2 (ja) * 2022-07-13 2025-11-12 株式会社村田製作所 電子部品
WO2024018514A1 (ja) * 2022-07-19 2024-01-25 オリンパスメディカルシステムズ株式会社 多層立体回路基板、内視鏡、および多層立体回路基板の製造方法
WO2024100981A1 (ja) * 2022-11-09 2024-05-16 株式会社村田製作所 回路モジュール、及び回路モジュールの実装方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5453403A (en) * 1994-10-24 1995-09-26 Chartered Semiconductor Manufacturing Pte, Ltd. Method of beveled contact opening formation
JP4800253B2 (ja) 2007-04-04 2011-10-26 新光電気工業株式会社 配線基板の製造方法
JP5121574B2 (ja) * 2008-05-28 2013-01-16 新光電気工業株式会社 配線基板及び半導体パッケージ
JP5479233B2 (ja) 2010-06-04 2014-04-23 新光電気工業株式会社 配線基板及びその製造方法
JP5981232B2 (ja) * 2012-06-06 2016-08-31 新光電気工業株式会社 半導体パッケージ、半導体装置及び半導体パッケージの製造方法

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US20170186677A1 (en) 2017-06-29
JP2017118067A (ja) 2017-06-29
US9899304B2 (en) 2018-02-20

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