JP6563367B2 - アクティブマトリクス基板、アクティブマトリクス基板の製造方法および表示装置 - Google Patents

アクティブマトリクス基板、アクティブマトリクス基板の製造方法および表示装置 Download PDF

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JP6563367B2
JP6563367B2 JP2016118475A JP2016118475A JP6563367B2 JP 6563367 B2 JP6563367 B2 JP 6563367B2 JP 2016118475 A JP2016118475 A JP 2016118475A JP 2016118475 A JP2016118475 A JP 2016118475A JP 6563367 B2 JP6563367 B2 JP 6563367B2
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oxide semiconductor
semiconductor layer
layer
electrode
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JP2017223815A (ja
JP2017223815A5 (enExample
Inventor
絵理 松尾
絵理 松尾
木下　智豊
智豊 木下
基博 豊田
基博 豊田
泰信 廣升
泰信 廣升
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Joled Inc
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Joled Inc
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H10D86/0212—Manufacture or treatment of multiple TFTs comprising manufacture, treatment or coating of substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/441—Interconnections, e.g. scanning lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Chemical & Material Sciences (AREA)
  • Mathematical Physics (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Electroluminescent Light Sources (AREA)
JP2016118475A 2016-06-15 2016-06-15 アクティブマトリクス基板、アクティブマトリクス基板の製造方法および表示装置 Active JP6563367B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2016118475A JP6563367B2 (ja) 2016-06-15 2016-06-15 アクティブマトリクス基板、アクティブマトリクス基板の製造方法および表示装置
US15/615,834 US10551704B2 (en) 2016-06-15 2017-06-07 Active matrix substrate method of manufacturing active matrix substrate, and display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016118475A JP6563367B2 (ja) 2016-06-15 2016-06-15 アクティブマトリクス基板、アクティブマトリクス基板の製造方法および表示装置

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JP2017223815A JP2017223815A (ja) 2017-12-21
JP2017223815A5 JP2017223815A5 (enExample) 2018-11-01
JP6563367B2 true JP6563367B2 (ja) 2019-08-21

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020202286A1 (ja) * 2019-03-29 2020-10-08 シャープ株式会社 表示デバイス、表示デバイスの製造方法
JP7284613B2 (ja) * 2019-03-29 2023-05-31 シャープ株式会社 アクティブマトリクス基板およびその製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
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JP2001015762A (ja) * 1999-07-02 2001-01-19 Seiko Epson Corp 薄膜半導体装置とその製造方法
US6828584B2 (en) * 2001-05-18 2004-12-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
JP5085859B2 (ja) * 2005-10-28 2012-11-28 株式会社ジャパンディスプレイイースト 画像表示装置及びその製造方法
EP1843194A1 (en) * 2006-04-06 2007-10-10 Semiconductor Energy Laboratory Co., Ltd. Liquid crystal display device, semiconductor device, and electronic appliance
KR101092483B1 (ko) * 2007-05-31 2011-12-13 캐논 가부시끼가이샤 산화물 반도체를 사용한 박막트랜지스터의 제조 방법
JP2009122256A (ja) * 2007-11-13 2009-06-04 Seiko Epson Corp 電気光学装置及び電子機器
JP5708910B2 (ja) 2010-03-30 2015-04-30 ソニー株式会社 薄膜トランジスタおよびその製造方法、並びに表示装置
US8409979B2 (en) * 2011-05-31 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US9653614B2 (en) * 2012-01-23 2017-05-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for manufacturing the same
TW201338173A (zh) * 2012-02-28 2013-09-16 Sony Corp 電晶體、製造電晶體之方法、顯示裝置及電子機器
CN104350533B (zh) 2013-03-18 2017-09-08 松下电器产业株式会社 薄膜半导体基板、发光面板以及薄膜半导体基板的制造方法
JP2015122417A (ja) * 2013-12-24 2015-07-02 ソニー株式会社 半導体装置およびその製造方法、並びに表示装置および電子機器

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US20170363926A1 (en) 2017-12-21
US10551704B2 (en) 2020-02-04

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