JP6534386B2 - スタック化されたダイの位置を制御するための技術 - Google Patents

スタック化されたダイの位置を制御するための技術 Download PDF

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JP6534386B2
JP6534386B2 JP2016522774A JP2016522774A JP6534386B2 JP 6534386 B2 JP6534386 B2 JP 6534386B2 JP 2016522774 A JP2016522774 A JP 2016522774A JP 2016522774 A JP2016522774 A JP 2016522774A JP 6534386 B2 JP6534386 B2 JP 6534386B2
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semiconductor die
assembly
stack
chip package
vertical
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JP2016533640A (ja
JP2016533640A5 (https=
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デイリンガー，マイケル・エイチ・エス
ホプキンス，アール・デイビッド
チョウ，アレックス
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オラクル・インターナショナル・コーポレイション
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
JP2016522774A 2013-10-21 2014-09-24 スタック化されたダイの位置を制御するための技術 Active JP6534386B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/059,302 2013-10-21
US14/059,302 US9209165B2 (en) 2013-10-21 2013-10-21 Technique for controlling positions of stacked dies
PCT/US2014/057237 WO2015060978A1 (en) 2013-10-21 2014-09-24 Technique for controlling positions of stacked dies

Publications (3)

Publication Number Publication Date
JP2016533640A JP2016533640A (ja) 2016-10-27
JP2016533640A5 JP2016533640A5 (https=) 2017-10-12
JP6534386B2 true JP6534386B2 (ja) 2019-06-26

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US (1) US9209165B2 (https=)
EP (1) EP3061131B1 (https=)
JP (1) JP6534386B2 (https=)
KR (1) KR102174120B1 (https=)
CN (1) CN105659382B (https=)
TW (1) TWI627682B (https=)
WO (1) WO2015060978A1 (https=)

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US9698093B2 (en) * 2015-08-24 2017-07-04 Nxp Usa,Inc. Universal BGA substrate
US10707171B2 (en) 2015-12-22 2020-07-07 Intel Corporation Ultra small molded module integrated with die by module-on-wafer assembly
US10234626B2 (en) * 2016-02-08 2019-03-19 Skorpios Technologies, Inc. Stepped optical bridge for connecting semiconductor waveguides
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KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
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US20150108615A1 (en) 2015-04-23
CN105659382A (zh) 2016-06-08
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