TWI627682B - 用於控制層疊晶片的位置之技術 - Google Patents

用於控制層疊晶片的位置之技術 Download PDF

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Publication number
TWI627682B
TWI627682B TW103134753A TW103134753A TWI627682B TW I627682 B TWI627682 B TW I627682B TW 103134753 A TW103134753 A TW 103134753A TW 103134753 A TW103134753 A TW 103134753A TW I627682 B TWI627682 B TW I627682B
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assembly
semiconductor die
semiconductor
vertical
steps
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TW103134753A
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TW201526122A (zh
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麥克 戴林格
爾 霍金斯
懷恩 周
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奧瑞可國際公司
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    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
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  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
TW103134753A 2013-10-21 2014-10-06 用於控制層疊晶片的位置之技術 TWI627682B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/059,302 2013-10-21
US14/059,302 US9209165B2 (en) 2013-10-21 2013-10-21 Technique for controlling positions of stacked dies

Publications (2)

Publication Number Publication Date
TW201526122A TW201526122A (zh) 2015-07-01
TWI627682B true TWI627682B (zh) 2018-06-21

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US (1) US9209165B2 (https=)
EP (1) EP3061131B1 (https=)
JP (1) JP6534386B2 (https=)
KR (1) KR102174120B1 (https=)
CN (1) CN105659382B (https=)
TW (1) TWI627682B (https=)
WO (1) WO2015060978A1 (https=)

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* Cited by examiner, † Cited by third party
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US9698093B2 (en) * 2015-08-24 2017-07-04 Nxp Usa,Inc. Universal BGA substrate
US10707171B2 (en) 2015-12-22 2020-07-07 Intel Corporation Ultra small molded module integrated with die by module-on-wafer assembly
US10234626B2 (en) * 2016-02-08 2019-03-19 Skorpios Technologies, Inc. Stepped optical bridge for connecting semiconductor waveguides
CN108878398B (zh) * 2017-05-16 2020-07-21 晟碟半导体（上海）有限公司 包括导电凸块互连的半导体器件
KR20190052957A (ko) * 2017-11-09 2019-05-17 에스케이하이닉스 주식회사 다이 오버시프트 지시 패턴을 포함하는 반도체 패키지
US11521862B2 (en) * 2017-12-15 2022-12-06 Chih-Liang Hu Process for fabricating circuit components in matrix batches
US20190279962A1 (en) * 2018-03-09 2019-09-12 Oracle International Corporation Method and apparatus for stacking warped chips to assemble three-dimensional integrated circuits
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