JP6516067B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP6516067B2
JP6516067B2 JP2018522230A JP2018522230A JP6516067B2 JP 6516067 B2 JP6516067 B2 JP 6516067B2 JP 2018522230 A JP2018522230 A JP 2018522230A JP 2018522230 A JP2018522230 A JP 2018522230A JP 6516067 B2 JP6516067 B2 JP 6516067B2
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metal layer
semiconductor substrate
metal
semiconductor device
patterns
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JPWO2017212578A1 (ja
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翔 鈴木
翔 鈴木
毅 大佐賀
毅 大佐賀
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Description

本発明は、基板の表面と裏面の両方にはんだ接合用の金属層が形成された半導体装置に関する。
電力用半導体装置として、高耐圧を有するＭＯＳＦＥＴ、ＩＧＢＴ又はＤｉｏｄｅが使用されている。電力用半導体装置は、低損失、高破壊耐量、小型化という良好な電気特性と低コストが求められている。近年、半導体基板を薄く研削することにより、良好な電気特性とチップ単価低減の両立が図られている。また、電力用半導体では、半導体基板の裏面電極上に金属層を形成し、金属層とはんだが反応することではんだ付けを行い、表面電極上には金属のワイヤボンディングを行う形態が一般的であった。しかし、低損失かつ小型化を実現するため、基板の表面と裏面の両方にはんだ接合用の金属層を形成し、両面はんだ付けを行う形態が増えつつある。
日本特開２０１５−５３４５５号公報
従来、半導体基板の表面側と裏面側で金属層の厚み又は材料が異なると、半導体基板が反ってしまい、クラックが生じたり、はんだボイドが発生したりといった組み立て性への悪影響が問題となっていた。また、半導体基板を薄く研削するトレンドとともに、半導体基板の反りが顕著になるというジレンマがあった。これに対して、両面に存在するはんだ接合用の金属膜を熱処理によって結晶化させることにより、両面から発生する応力を打ち消して反りを抑える技術が開示されている（例えば、特許文献１参照）。しかし、表面の金属層を形成した後に熱処理が必要である。また、金属層が酸化して組み立て時のはんだ濡れ性を阻害し、組み立て性を悪化させるという問題もある。
本発明は、上述のような課題を解決するためになされたもので、その目的ははんだ接合用の金属層を酸化させることなく、組み立て性を改善することができる半導体装置を得るものである。
本発明に係る半導体装置は、互いに対向する表面及び裏面を有する半導体基板と、前記半導体基板の前記表面に形成された第１の金属層と、前記第１の金属層上に形成されたはんだ接合用の第２の金属層と、前記半導体基板の前記裏面に形成された第３の金属層と、前記第３の金属層上に形成されたはんだ接合用の第４の金属層とを備え、前記第２の金属層の厚みは前記第４の金属層の厚みより厚く、前記第１及び第３の金属層はパターン分割されておらず、前記第２の金属層は、パターン分割され、前記第１の金属層を介して互いに電気的に接続された複数の金属層を有し、前記第４の金属層は、パターン分割され、前記第３の金属層を介して互いに電気的に接続された複数の金属層を有し、前記第２の金属層のパターン分割数は前記第４の金属層のパターン分割数より多いことを特徴とする。
本発明では、第１、第３及び第４の金属層はパターン分割されていないが、第２の金属層はパターン分割されている。これにより、厚い第２の金属層が温度変化によって膨張又は収縮する際に発生する応力はパターン間の隙間によって緩和されるため、半導体基板が受ける応力が小さくなり、半導体基板の反りを抑えることができる。この結果、組み立て性を改善することができる。
本発明の実施の形態１に係る半導体装置を示す断面図である。 比較例に係る半導体装置を示す断面図である。 本発明の実施の形態２に係る半導体装置を示す断面図である。 本発明の実施の形態３に係る半導体装置を示す断面図である。
本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態１．
図１は、本発明の実施の形態１に係る半導体装置を示す断面図である。半導体基板１は互いに対向する表面及び裏面を有する。第１の金属層２が半導体基板１の表面に形成され、半導体基板１の表面に直接的に接して電気的に接続されている。第１の金属層２は例えばＩＧＢＴのエミッタ電極又はダイオードのアノード電極などである。はんだ接合用の第２の金属層３が第１の金属層２上に形成されている。第２の金属層３の酸化を防止するための金属層４が第２の金属層３上に形成されている。
第３の金属層５が半導体基板１の裏面に形成され、半導体基板１の裏面に直接的に接して電気的に接続されている。第３の金属層５は例えばＩＧＢＴのコレクタ電極又はダイオードのカソード電極などである。はんだ接合用の第４の金属層６が第３の金属層５上に形成されている。第４の金属層６の酸化を防止するための金属層７が第４の金属層６上に形成されている。
第２の金属層３の厚みは第４の金属層６の厚みより厚い。はんだ接合用の第２及び第４の金属層３，６は少なくともニッケルを含み、第１及び第３の金属層２，５よりもはんだ濡れ性が高い。第１、第３及び第４の金属層２，５，６は半導体基板１の表面又は裏面に一様に形成されてパターン分割されていない。第２の金属層３は、パターン分割され、第１の金属層２を介して互いに電気的に接続された複数の金属層を有する。
続いて本実施の形態の効果を比較例と比較して説明する。図２は、比較例に係る半導体装置を示す断面図である。第２及び第４の金属層３，６は温度が上昇すると膨張し、温度が低下すると収縮を起こす。比較例では、表面側の厚い第２の金属層３が半導体基板１の表面に一様に形成されてパターン分割されていない。このため、温度変化による膨張と収縮は裏面側の第４の金属層６よりも表面側の厚い第２の金属層３で大きく発生する。従って、表面側の第２の金属層３が半導体基板１に与える応力と、裏面側の第４の金属層６が半導体基板１に与える応力に差が生じ、半導体基板１に反りが発生する。
これに対し、本実施の形態では、第１、第３及び第４の金属層２，５，６はパターン分割されていないが、第２の金属層３はパターン分割されている。これにより、厚い第２の金属層３が温度変化によって膨張又は収縮する際に発生する応力はパターン間の隙間によって緩和されるため、半導体基板１が受ける応力が小さくなり、半導体基板１の反りを抑えることができる。また、応力を緩和するために第２及び第４の金属層３，６を熱処理により結晶化する必要が無いため、酸化してはんだ濡れ性が低下することはない。この結果、組み立て性を改善することができる。
実施の形態２．
図３は、本発明の実施の形態２に係る半導体装置を示す断面図である。実施の形態１と異なり、第２及び第４の金属層３，６の両方がパターン分割されている。即ち、第２の金属層３は、パターン分割され、第１の金属層２を介して互いに電気的に接続された複数の金属層を有する。そして、第４の金属層６も、パターン分割され、第３の金属層５を介して互いに電気的に接続された複数の金属層を有する。
第２の金属層３のパターン分割数Ａは第４の金属層６のパターン分割数Ｂより多い（Ａ＞Ｂ）。これにより、表面で発生する応力は裏面で発生する応力よりも緩和されやすくなり、半導体基板１が受ける応力の差も小さくなるため、半導体基板１の反りを抑えることができる。この結果、組み立て性を改善することができる。
実施の形態３．
図４は、本発明の実施の形態３に係る半導体装置を示す断面図である。実施の形態１と異なり、第２の金属層３も半導体基板１の表面に一様に形成されてパターン分割されていない。第２及び第４の金属層３，６は、無電解めっきで形成されたリンを含む非晶質のニッケルである。
ここで、はんだ接合用の金属として一般的にニッケルが使用されている。厚いニッケル層を形成する手法として無電解めっきが知られている。無電解めっきは還元剤を用いることで金属が析出する機構であり、還元剤として次亜リン酸を用いることが知られている。次亜リン酸を用いた無電解めっきでニッケル層を形成する場合、ニッケルは次亜リン酸に含まれるリンと合金を作りながら、非晶質の状態で析出する。
上述の通り、第２及び第４の金属層３，６は温度変化によって膨張と収縮を起こすが、温度変化による膨張の度合を示す物性値は線膨脹係数である。ニッケルとリンの合金の線膨脹係数はニッケル中に含まれるリンの濃度によって変化することが知られており、含まれるリンの濃度が高いほど線膨脹係数は小さくなる。
本実施の形態では、第２の金属層３のリン濃度αが第４の金属層６のリン濃度βより大きい（α＞β）。これにより、温度変化によって表面の第２の金属層３が単位体積当たりに膨張と収縮をする大きさは、裏面の第４の金属層６のそれよりも小さくなる。従って、両面のリン濃度が同じである場合と比較して、温度変化が発生した際に半導体基板１が受ける応力の差も小さくなるため、半導体基板１の反りを抑えることができる。この結果、組み立て性を改善することができる。
上述の実施の形態１〜３において半導体基板１として一般的にＳｉ基板が用いられるが、これに限らずＳｉ基板より硬い炭化ケイ素（ＳｉＣ）基板又は窒化ガリウム（ＧａＮ）基板を用いることで、半導体基板１の反りを抑えることができる。さらに、ＳｉＣ基板又はＧａＮ基板を用いたパワー半導体素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体モジュールも小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
１ 半導体基板、２ 第１の金属層、３ 第２の金属層、５ 第３の金属層、６ 第４の金属層

Claims (5)

  1. 互いに対向する表面及び裏面を有する半導体基板と、
    前記半導体基板の前記表面に形成された第１の金属層と、
    前記第１の金属層上に形成されたはんだ接合用の第２の金属層と、
    前記半導体基板の前記裏面に形成された第３の金属層と、
    前記第３の金属層上に形成されたはんだ接合用の第４の金属層とを備え、
    前記第２の金属層の厚みは前記第４の金属層の厚みより厚く、
    前記第１及び第３の金属層はパターン分割されておらず、
    前記第２の金属層は、パターン分割され、前記第１の金属層を介して互いに電気的に接続された複数の金属層を有し、
    前記第４の金属層は、パターン分割され、前記第３の金属層を介して互いに電気的に接続された複数の金属層を有し、
    前記第２の金属層のパターン分割数は前記第４の金属層のパターン分割数より多いことを特徴とする半導体装置。
  2. 前記第２及び第４の金属層はニッケルを含むことを特徴とする請求項１に記載の半導体装置。
  3. 互いに対向する表面及び裏面を有する半導体基板と、
    前記半導体基板の前記表面に形成された第１の金属層と、
    前記第１の金属層上に形成されたはんだ接合用の第２の金属層と、
    前記半導体基板の前記裏面に形成された第３の金属層と、
    前記第３の金属層上に形成されたはんだ接合用の第４の金属層とを備え、
    前記第２の金属層の厚みは前記第４の金属層の厚みより厚く、
    前記第２及び第４の金属層はリンを含む非晶質のニッケルであり、
    前記第２の金属層のリン濃度は前記第４の金属層のリン濃度より大きいことを特徴とする半導体装置。
  4. 前記第２及び第４の金属層は結晶化していないことを特徴とする請求項１〜３の何れか１項に記載の半導体装置。
  5. 前記半導体基板はＳｉＣ基板又はＧａＮ基板であることを特徴とする請求項１〜４の何れか１項に記載の半導体装置。
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