WO2017212578A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2017212578A1
WO2017212578A1 PCT/JP2016/067080 JP2016067080W WO2017212578A1 WO 2017212578 A1 WO2017212578 A1 WO 2017212578A1 JP 2016067080 W JP2016067080 W JP 2016067080W WO 2017212578 A1 WO2017212578 A1 WO 2017212578A1
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WIPO (PCT)
Prior art keywords
metal layer
semiconductor substrate
metal
divided
layers
Prior art date
Application number
PCT/JP2016/067080
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English (en)
French (fr)
Inventor
翔 鈴木
毅 大佐賀
Original Assignee
三菱電機株式会社
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Publication date
Application filed by 三菱電機株式会社 filed Critical 三菱電機株式会社
Priority to US16/082,244 priority Critical patent/US10685932B2/en
Priority to DE112016006952.9T priority patent/DE112016006952T5/de
Priority to JP2018522230A priority patent/JP6516067B2/ja
Priority to CN201690001686.9U priority patent/CN209591978U/zh
Priority to PCT/JP2016/067080 priority patent/WO2017212578A1/ja
Publication of WO2017212578A1 publication Critical patent/WO2017212578A1/ja

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Definitions

  • the present invention relates to a semiconductor device in which a metal layer for solder bonding is formed on both the front surface and the back surface of a substrate.
  • a MOSFET, IGBT, or Diode having a high breakdown voltage is used as a power semiconductor device.
  • Power semiconductor devices are required to have good electrical characteristics such as low loss, high breakdown tolerance, and miniaturization, and low cost.
  • a semiconductor substrate is thinly ground to achieve both good electrical characteristics and a reduction in chip unit cost.
  • a form in which a metal layer for solder bonding is formed on both the front surface and the back surface of a substrate and double-sided soldering is increasing.
  • the present invention has been made to solve the above-described problems, and an object of the present invention is to obtain a semiconductor device capable of improving the assembling property without oxidizing the metal layer for solder joining.
  • a semiconductor device includes a semiconductor substrate having front and back surfaces facing each other, a first metal layer formed on the surface of the semiconductor substrate, and a solder joint formed on the first metal layer.
  • the first, third and fourth metal layers are not divided into patterns, but the second metal layer is divided into patterns.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention.
  • the semiconductor substrate 1 has a front surface and a back surface that face each other.
  • a first metal layer 2 is formed on the surface of the semiconductor substrate 1 and is in direct contact with and electrically connected to the surface of the semiconductor substrate 1.
  • the first metal layer 2 is, for example, an IGBT emitter electrode or a diode anode electrode.
  • a second metal layer 3 for solder bonding is formed on the first metal layer 2.
  • a metal layer 4 for preventing oxidation of the second metal layer 3 is formed on the second metal layer 3.
  • the third metal layer 5 is formed on the back surface of the semiconductor substrate 1 and is in direct contact with and electrically connected to the back surface of the semiconductor substrate 1.
  • the third metal layer 5 is, for example, an IGBT collector electrode or a diode cathode electrode.
  • a fourth metal layer 6 for solder bonding is formed on the third metal layer 5.
  • a metal layer 7 for preventing oxidation of the fourth metal layer 6 is formed on the fourth metal layer 6.
  • the thickness of the second metal layer 3 is thicker than the thickness of the fourth metal layer 6.
  • the second and fourth metal layers 3 and 6 for solder bonding contain at least nickel and have higher solder wettability than the first and third metal layers 2 and 5.
  • the first, third, and fourth metal layers 2, 5, 6 are uniformly formed on the front surface or the back surface of the semiconductor substrate 1 and are not divided into patterns.
  • the second metal layer 3 includes a plurality of metal layers that are divided into patterns and are electrically connected to each other via the first metal layer 2.
  • FIG. 2 is a cross-sectional view showing a semiconductor device according to a comparative example.
  • the second and fourth metal layers 3 and 6 expand when the temperature increases, and contract when the temperature decreases.
  • the thick second metal layer 3 on the surface side is uniformly formed on the surface of the semiconductor substrate 1 and is not divided into patterns. For this reason, expansion and contraction due to temperature change occur more greatly in the second metal layer 3 that is thicker on the front side than the fourth metal layer 6 on the back side. Therefore, there is a difference between the stress applied to the semiconductor substrate 1 by the second metal layer 3 on the front surface side and the stress applied to the semiconductor substrate 1 from the fourth metal layer 6 on the back surface side, and the semiconductor substrate 1 is warped.
  • the first, third, and fourth metal layers 2, 5, and 6 are not divided into patterns, but the second metal layer 3 is divided into patterns.
  • the stress generated when the thick second metal layer 3 expands or contracts due to a temperature change is relieved by the gap between the patterns, so that the stress received by the semiconductor substrate 1 is reduced, and the warp of the semiconductor substrate 1 is reduced. Can be suppressed.
  • the solder wettability is not deteriorated due to oxidation. As a result, the assemblability can be improved.
  • FIG. FIG. 3 is a sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • both the second and fourth metal layers 3 and 6 are divided into patterns. That is, the second metal layer 3 has a plurality of metal layers that are pattern-divided and electrically connected to each other via the first metal layer 2.
  • the fourth metal layer 6 also has a plurality of metal layers that are pattern-divided and electrically connected to each other via the third metal layer 5.
  • the pattern division number A of the second metal layer 3 is larger than the pattern division number B of the fourth metal layer 6 (A> B).
  • FIG. FIG. 4 is a cross-sectional view showing a semiconductor device according to Embodiment 3 of the present invention.
  • the second metal layer 3 is also uniformly formed on the surface of the semiconductor substrate 1 and is not divided into patterns.
  • the second and fourth metal layers 3 and 6 are amorphous nickel containing phosphorus formed by electroless plating.
  • Electroless plating is known as a technique for forming a thick nickel layer. Electroless plating is a mechanism in which metal is deposited by using a reducing agent, and it is known to use hypophosphorous acid as the reducing agent. When a nickel layer is formed by electroless plating using hypophosphorous acid, nickel precipitates in an amorphous state while forming an alloy with phosphorus contained in hypophosphorous acid.
  • the second and fourth metal layers 3 and 6 expand and contract due to temperature change, but a physical property value indicating the degree of expansion due to temperature change is a linear expansion coefficient. It is known that the linear expansion coefficient of an alloy of nickel and phosphorus varies depending on the concentration of phosphorus contained in nickel, and the higher the concentration of phosphorus contained, the smaller the linear expansion coefficient.
  • the phosphorus concentration ⁇ of the second metal layer 3 is larger than the phosphorus concentration ⁇ of the fourth metal layer 6 ( ⁇ > ⁇ ).
  • a Si substrate is generally used as the semiconductor substrate 1.
  • the present invention is not limited to this, and by using a silicon carbide (SiC) substrate or a gallium nitride (GaN) substrate that is harder than the Si substrate, Warpage of the substrate 1 can be suppressed.
  • a power semiconductor element using a SiC substrate or a GaN substrate can be miniaturized because of its high voltage resistance and allowable current density. By using this miniaturized element, a semiconductor module incorporating this element can also be miniaturized.
  • the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized and the water cooling part can be air cooled, so that the semiconductor module can be further miniaturized.
  • the power loss of the element is low and the efficiency is high, the efficiency of the semiconductor module can be increased.

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Abstract

 半導体基板(1)は互いに対向する表面及び裏面を有する。第1の金属層(2)が半導体基板(1)の表面に形成されている。はんだ接合用の第2の金属層(3)が第1の金属層(2)上に形成されている。第3の金属層(5)が半導体基板1の裏面に形成されている。はんだ接合用の第4の金属層(6)が第3の金属層(5)上に形成されている。第2の金属層(3)の厚みは第4の金属層(6)の厚みより厚い。第1、第3及び第4の金属層(2,5,6)はパターン分割されていない。第2の金属層(3)は、パターン分割され、第1の金属層(2)を介して互いに電気的に接続された複数の金属層を有する。

Description

半導体装置
 本発明は、基板の表面と裏面の両方にはんだ接合用の金属層が形成された半導体装置に関する。
 電力用半導体装置として、高耐圧を有するMOSFET、IGBT又はDiodeが使用されている。電力用半導体装置は、低損失、高破壊耐量、小型化という良好な電気特性と低コストが求められている。近年、半導体基板を薄く研削することにより、良好な電気特性とチップ単価低減の両立が図られている。また、電力用半導体では、半導体基板の裏面電極上に金属層を形成し、金属層とはんだが反応することではんだ付けを行い、表面電極上には金属のワイヤボンディングを行う形態が一般的であった。しかし、低損失かつ小型化を実現するため、基板の表面と裏面の両方にはんだ接合用の金属層を形成し、両面はんだ付けを行う形態が増えつつある。
日本特開2015-53455号公報
 従来、半導体基板の表面側と裏面側で金属層の厚み又は材料が異なると、半導体基板が反ってしまい、クラックが生じたり、はんだボイドが発生したりといった組み立て性への悪影響が問題となっていた。また、半導体基板を薄く研削するトレンドとともに、半導体基板の反りが顕著になるというジレンマがあった。これに対して、両面に存在するはんだ接合用の金属膜を熱処理によって結晶化させることにより、両面から発生する応力を打ち消して反りを抑える技術が開示されている(例えば、特許文献1参照)。しかし、表面の金属層を形成した後に熱処理が必要である。また、金属層が酸化して組み立て時のはんだ濡れ性を阻害し、組み立て性を悪化させるという問題もある。
 本発明は、上述のような課題を解決するためになされたもので、その目的ははんだ接合用の金属層を酸化させることなく、組み立て性を改善することができる半導体装置を得るものである。
 本発明に係る半導体装置は、互いに対向する表面及び裏面を有する半導体基板と、前記半導体基板の前記表面に形成された第1の金属層と、前記第1の金属層上に形成されたはんだ接合用の第2の金属層と、前記半導体基板の前記裏面に形成された第3の金属層と、前記第3の金属層上に形成されたはんだ接合用の第4の金属層とを備え、前記第2の金属層の厚みは前記第4の金属層の厚みより厚く、前記第1、第3及び第4の金属層はパターン分割されておらず、前記第2の金属層は、パターン分割され、前記第1の金属層を介して互いに電気的に接続された複数の金属層を有することを特徴とする。
 本発明では、第1、第3及び第4の金属層はパターン分割されていないが、第2の金属層はパターン分割されている。これにより、厚い第2の金属層が温度変化によって膨張又は収縮する際に発生する応力はパターン間の隙間によって緩和されるため、半導体基板が受ける応力が小さくなり、半導体基板の反りを抑えることができる。この結果、組み立て性を改善することができる。
本発明の実施の形態1に係る半導体装置を示す断面図である。 比較例に係る半導体装置を示す断面図である。 本発明の実施の形態2に係る半導体装置を示す断面図である。 本発明の実施の形態3に係る半導体装置を示す断面図である。
 本発明の実施の形態に係る半導体装置について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。
実施の形態1.
 図1は、本発明の実施の形態1に係る半導体装置を示す断面図である。半導体基板1は互いに対向する表面及び裏面を有する。第1の金属層2が半導体基板1の表面に形成され、半導体基板1の表面に直接的に接して電気的に接続されている。第1の金属層2は例えばIGBTのエミッタ電極又はダイオードのアノード電極などである。はんだ接合用の第2の金属層3が第1の金属層2上に形成されている。第2の金属層3の酸化を防止するための金属層4が第2の金属層3上に形成されている。
 第3の金属層5が半導体基板1の裏面に形成され、半導体基板1の裏面に直接的に接して電気的に接続されている。第3の金属層5は例えばIGBTのコレクタ電極又はダイオードのカソード電極などである。はんだ接合用の第4の金属層6が第3の金属層5上に形成されている。第4の金属層6の酸化を防止するための金属層7が第4の金属層6上に形成されている。
 第2の金属層3の厚みは第4の金属層6の厚みより厚い。はんだ接合用の第2及び第4の金属層3,6は少なくともニッケルを含み、第1及び第3の金属層2,5よりもはんだ濡れ性が高い。第1、第3及び第4の金属層2,5,6は半導体基板1の表面又は裏面に一様に形成されてパターン分割されていない。第2の金属層3は、パターン分割され、第1の金属層2を介して互いに電気的に接続された複数の金属層を有する。
 続いて本実施の形態の効果を比較例と比較して説明する。図2は、比較例に係る半導体装置を示す断面図である。第2及び第4の金属層3,6は温度が上昇すると膨張し、温度が低下すると収縮を起こす。比較例では、表面側の厚い第2の金属層3が半導体基板1の表面に一様に形成されてパターン分割されていない。このため、温度変化による膨張と収縮は裏面側の第4の金属層6よりも表面側の厚い第2の金属層3で大きく発生する。従って、表面側の第2の金属層3が半導体基板1に与える応力と、裏面側の第4の金属層6が半導体基板1に与える応力に差が生じ、半導体基板1に反りが発生する。
 これに対し、本実施の形態では、第1、第3及び第4の金属層2,5,6はパターン分割されていないが、第2の金属層3はパターン分割されている。これにより、厚い第2の金属層3が温度変化によって膨張又は収縮する際に発生する応力はパターン間の隙間によって緩和されるため、半導体基板1が受ける応力が小さくなり、半導体基板1の反りを抑えることができる。また、応力を緩和するために第2及び第4の金属層3,6を熱処理により結晶化する必要が無いため、酸化してはんだ濡れ性が低下することはない。この結果、組み立て性を改善することができる。
実施の形態2.
 図3は、本発明の実施の形態2に係る半導体装置を示す断面図である。実施の形態1と異なり、第2及び第4の金属層3,6の両方がパターン分割されている。即ち、第2の金属層3は、パターン分割され、第1の金属層2を介して互いに電気的に接続された複数の金属層を有する。そして、第4の金属層6も、パターン分割され、第3の金属層5を介して互いに電気的に接続された複数の金属層を有する。
 第2の金属層3のパターン分割数Aは第4の金属層6のパターン分割数Bより多い(A>B)。これにより、表面で発生する応力は裏面で発生する応力よりも緩和されやすくなり、半導体基板1が受ける応力の差も小さくなるため、半導体基板1の反りを抑えることができる。この結果、組み立て性を改善することができる。
実施の形態3.
 図4は、本発明の実施の形態3に係る半導体装置を示す断面図である。実施の形態1と異なり、第2の金属層3も半導体基板1の表面に一様に形成されてパターン分割されていない。第2及び第4の金属層3,6は、無電解めっきで形成されたリンを含む非晶質のニッケルである。
 ここで、はんだ接合用の金属として一般的にニッケルが使用されている。厚いニッケル層を形成する手法として無電解めっきが知られている。無電解めっきは還元剤を用いることで金属が析出する機構であり、還元剤として次亜リン酸を用いることが知られている。次亜リン酸を用いた無電解めっきでニッケル層を形成する場合、ニッケルは次亜リン酸に含まれるリンと合金を作りながら、非晶質の状態で析出する。
 上述の通り、第2及び第4の金属層3,6は温度変化によって膨張と収縮を起こすが、温度変化による膨張の度合を示す物性値は線膨脹係数である。ニッケルとリンの合金の線膨脹係数はニッケル中に含まれるリンの濃度によって変化することが知られており、含まれるリンの濃度が高いほど線膨脹係数は小さくなる。
 本実施の形態では、第2の金属層3のリン濃度αが第4の金属層6のリン濃度βより大きい(α>β)。これにより、温度変化によって表面の第2の金属層3が単位体積当たりに膨張と収縮をする大きさは、裏面の第4の金属層6のそれよりも小さくなる。従って、両面のリン濃度が同じである場合と比較して、温度変化が発生した際に半導体基板1が受ける応力の差も小さくなるため、半導体基板1の反りを抑えることができる。この結果、組み立て性を改善することができる。
 上述の実施の形態1~3において半導体基板1として一般的にSi基板が用いられるが、これに限らずSi基板より硬い炭化ケイ素(SiC)基板又は窒化ガリウム(GaN)基板を用いることで、半導体基板1の反りを抑えることができる。さらに、SiC基板又はGaN基板を用いたパワー半導体素子は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ半導体モジュールも小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、半導体モジュールを更に小型化できる。また、素子の電力損失が低く高効率であるため、半導体モジュールを高効率化できる。
1 半導体基板、2 第1の金属層、3 第2の金属層、5 第3の金属層、6 第4の金属層

Claims (6)

  1.  互いに対向する表面及び裏面を有する半導体基板と、
     前記半導体基板の前記表面に形成された第1の金属層と、
     前記第1の金属層上に形成されたはんだ接合用の第2の金属層と、
     前記半導体基板の前記裏面に形成された第3の金属層と、
     前記第3の金属層上に形成されたはんだ接合用の第4の金属層とを備え、
     前記第2の金属層の厚みは前記第4の金属層の厚みより厚く、
     前記第1、第3及び第4の金属層はパターン分割されておらず、
     前記第2の金属層は、パターン分割され、前記第1の金属層を介して互いに電気的に接続された複数の金属層を有することを特徴とする半導体装置。
  2.  互いに対向する表面及び裏面を有する半導体基板と、
     前記半導体基板の前記表面に形成された第1の金属層と、
     前記第1の金属層上に形成されたはんだ接合用の第2の金属層と、
     前記半導体基板の前記裏面に形成された第3の金属層と、
     前記第3の金属層上に形成されたはんだ接合用の第4の金属層とを備え、
     前記第2の金属層の厚みは前記第4の金属層の厚みより厚く、
     前記第1及び第3の金属層はパターン分割されておらず、
     前記第2の金属層は、パターン分割され、前記第1の金属層を介して互いに電気的に接続された複数の金属層を有し、
     前記第4の金属層は、パターン分割され、前記第3の金属層を介して互いに電気的に接続された複数の金属層を有し、
     前記第2の金属層のパターン分割数は前記第4の金属層のパターン分割数より多いことを特徴とする半導体装置。
  3.  前記第2及び第4の金属層はニッケルを含むことを特徴とする請求項1又は2に記載の半導体装置。
  4.  互いに対向する表面及び裏面を有する半導体基板と、
     前記半導体基板の前記表面に形成された第1の金属層と、
     前記第1の金属層上に形成されたはんだ接合用の第2の金属層と、
     前記半導体基板の前記裏面に形成された第3の金属層と、
     前記第3の金属層上に形成されたはんだ接合用の第4の金属層とを備え、
     前記第2の金属層の厚みは前記第4の金属層の厚みより厚く、
     前記第2及び第4の金属層はリンを含む非晶質のニッケルであり、
     前記第2の金属層のリン濃度は前記第4の金属層のリン濃度より大きいことを特徴とする半導体装置。
  5.  前記第2及び第4の金属層は結晶化していないことを特徴とする請求項1~4の何れか1項に記載の半導体装置。
  6.  前記半導体基板はSiC基板又はGaN基板であることを特徴とする請求項1~5の何れか1項に記載の半導体装置。
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