JP6480593B2 - 薄膜トランジスタの製造方法及び薄膜トランジスタ - Google Patents
薄膜トランジスタの製造方法及び薄膜トランジスタ Download PDFInfo
- Publication number
- JP6480593B2 JP6480593B2 JP2017540438A JP2017540438A JP6480593B2 JP 6480593 B2 JP6480593 B2 JP 6480593B2 JP 2017540438 A JP2017540438 A JP 2017540438A JP 2017540438 A JP2017540438 A JP 2017540438A JP 6480593 B2 JP6480593 B2 JP 6480593B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon layer
- silicon
- layer
- etching
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 51
- 239000010409 thin film Substances 0.000 title claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 229
- 229910052710 silicon Inorganic materials 0.000 claims description 219
- 239000010703 silicon Substances 0.000 claims description 219
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 101
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 59
- 238000005530 etching Methods 0.000 claims description 59
- 229920002120 photoresistant polymer Polymers 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 50
- 239000010408 film Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 17
- 238000004380 ashing Methods 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 description 23
- 238000000137 annealing Methods 0.000 description 12
- 238000000206 photolithography Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 238000004140 cleaning Methods 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000002093 peripheral effect Effects 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02592—Microstructure amorphous
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
- H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1229—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different crystal properties within a device or between different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Optics & Photonics (AREA)
- Thin Film Transistor (AREA)
- Recrystallisation Techniques (AREA)
Description
<実施形態1>
まず、従来のTFT及びその製造方法について説明する。図1は、従来のTFTの要部の模式的断面図である。ガラス基板等の絶縁性の基板51の表面にゲート電極52が形成されており、ゲート電極52を覆って基板51上にゲート絶縁膜53が形成されている。ゲート絶縁膜53の表面の内でゲート電極52の上側には、第1の半導体層54が形成されている。第1の半導体層54は、多結晶シリコンでなる多結晶シリコン部541と非晶質シリコンでなる非晶質シリコン部542とを含んでいる。非晶質シリコン部542は、多結晶シリコン部541の周囲に配置されている。第1の半導体層54の表面には、非晶質シリコンでなる第2の半導体層55が形成されている。
実施形態2に係るTFTの構造は、実施形態1と同様である。図9は、実施形態2に係るTFTの製造方法を示す工程図である。図10A及び図10Bは、実施形態2に係るTFTの製造工程の一部を示す模式的断面図である。実施形態1と同様、図7Aに示すように、基板11上にゲート電極12を形成し(S201)、ゲート電極12を覆って基板11の表面にゲート絶縁膜13を形成し(S202)、ゲート絶縁膜13の表面に非晶質シリコンからなる第1シリコン層14を形成する(S203)。次に、実施形態1と同様、図7Bに示すように、アニール処理により、第1シリコン層14の内、第1領域141を含み第1領域141よりも広い範囲を多結晶シリコンへ変化させ、多結晶シリコン部142を生成する(S204)。
実施形態1及び2では、TFT中の第1シリコン層14が多結晶シリコンで構成された形態を示したが、実施形態3では、第1シリコン層14中に非晶質シリコン及び多結晶シリコンが混在した形態を示す。
12 ゲート電極
13 ゲート絶縁膜
14 第1シリコン層
141 第1領域
142 多結晶シリコン部
143 非晶質シリコン部
15 第2シリコン層
151 第2領域
16 n+Si層
17 ソース電極
18 ドレイン電極
2、23、3、41、42 フォトレジスト
Claims (4)
- 薄膜トランジスタの製造方法において、
基板の表面にゲート電極を形成する工程と、
ゲート電極が形成された前記基板の表面に絶縁膜を形成する工程と、
前記絶縁膜を形成した後に、非晶質シリコンからなる第1シリコン層を形成する工程と、
前記第1シリコン層上で、所定の面積を有する所定領域内の一部又は全部から前記所定領域の外部にかけてエネルギービームを照射して、前記第1シリコン層中の前記エネルギービームを照射した部分を多結晶シリコンに変化させる工程と、
前記所定領域を残すように前記第1シリコン層をエッチングする第1エッチング工程と、
前記第1シリコン層の前記所定領域を覆って、非晶質シリコンからなる第2シリコン層を、前記第1シリコン層の前記所定領域よりも広い範囲に形成する工程と、
前記第1シリコン層の前記所定領域を覆っており前記第1シリコン層の前記所定領域よりも広い部分を残すように、前記第2シリコン層をエッチングする第2エッチング工程と、
エッチング後の前記第1シリコン層及び前記第2シリコン層をチャネル層にしたソース電極及びドレイン電極を形成する電極形成工程とを含むこと
を特徴とする薄膜トランジスタの製造方法。 - 前記電極形成工程は、前記第1シリコン層中の多結晶シリコンの部分と前記ソース電極及び前記ドレイン電極の少なくとも一方とを前記基板に射影した位置が重なるように、前記ソース電極及び前記ドレイン電極を形成すること
を特徴とする請求項1に記載の薄膜トランジスタの製造方法。 - 前記第1エッチング工程は、
前記第1シリコン層の前記所定領域及び前記所定領域に隣接する領域を保護し、前記所定領域に隣接する領域を保護する部分の厚さが前記所定領域を保護する部分の厚さよりも薄くなっている第1フォトレジストを、多階調のフォトマスクを用いて形成する工程と、
アッシングにより、前記第1フォトレジストから、前記所定領域に隣接する領域を保護する部分を除去する工程と、
前記第1シリコン層から、前記第1フォトレジストの残存部分で保護されていない部分を除去する工程とを含み、
前記第2エッチング工程は、
前記第1エッチング工程と同一のフォトマスクを用いて、前記第2シリコン層上の前記第1シリコン層の前記所定領域を覆った領域及び該領域に隣接する領域を保護する第2フォトレジストを形成する工程と、
前記第2シリコン層から、前記第2フォトレジストで保護されていない部分を除去する工程とを含むこと
を特徴とする請求項1又は2に記載の薄膜トランジスタの製造方法。 - 前記第1エッチング工程及び前記第2エッチング工程は、
同一のフォトマスクを用いてフォトレジストを形成する工程を含んでおり、
エッチング後の第1シリコン層の面積よりもエッチング後の第2シリコン層の面積の方が広くなるように、エッチングの条件を異ならせてあること
を特徴とする請求項1又は2に記載の薄膜トランジスタの製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/076705 WO2017046948A1 (ja) | 2015-09-18 | 2015-09-18 | 薄膜トランジスタの製造方法及び薄膜トランジスタ |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2017046948A1 JPWO2017046948A1 (ja) | 2018-08-02 |
JP6480593B2 true JP6480593B2 (ja) | 2019-03-13 |
Family
ID=58288480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017540438A Expired - Fee Related JP6480593B2 (ja) | 2015-09-18 | 2015-09-18 | 薄膜トランジスタの製造方法及び薄膜トランジスタ |
Country Status (4)
Country | Link |
---|---|
US (1) | US10256350B2 (ja) |
JP (1) | JP6480593B2 (ja) |
CN (1) | CN108028283B (ja) |
WO (1) | WO2017046948A1 (ja) |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0473988A1 (en) * | 1990-08-29 | 1992-03-11 | International Business Machines Corporation | Method of fabricating a thin film transistor having amorphous/polycrystalline semiconductor channel region |
JP2008140984A (ja) * | 2006-12-01 | 2008-06-19 | Sharp Corp | 半導体素子、半導体素子の製造方法、及び表示装置 |
JP5226259B2 (ja) * | 2007-08-21 | 2013-07-03 | 株式会社ジャパンディスプレイイースト | 液晶表示装置 |
JP5470519B2 (ja) * | 2009-07-24 | 2014-04-16 | 株式会社ブイ・テクノロジー | 薄膜トランジスタ、その製造方法及び液晶表示装置 |
JP5421357B2 (ja) * | 2010-05-11 | 2014-02-19 | パナソニック株式会社 | 表示装置用薄膜半導体装置及びその製造方法 |
CN102473737B (zh) * | 2010-06-22 | 2014-07-23 | 松下电器产业株式会社 | 发光显示装置及其制造方法 |
JP2012114131A (ja) * | 2010-11-22 | 2012-06-14 | Panasonic Corp | 薄膜トランジスタ、その製造方法、および表示装置 |
CN102842619B (zh) * | 2012-09-03 | 2016-08-03 | 南京中电熊猫液晶显示科技有限公司 | 一种半导体装置及其制造方法 |
-
2015
- 2015-09-18 WO PCT/JP2015/076705 patent/WO2017046948A1/ja active Application Filing
- 2015-09-18 JP JP2017540438A patent/JP6480593B2/ja not_active Expired - Fee Related
- 2015-09-18 CN CN201580083210.4A patent/CN108028283B/zh active Active
-
2018
- 2018-03-16 US US15/923,546 patent/US10256350B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US10256350B2 (en) | 2019-04-09 |
WO2017046948A1 (ja) | 2017-03-23 |
CN108028283A (zh) | 2018-05-11 |
CN108028283B (zh) | 2021-03-02 |
US20180204957A1 (en) | 2018-07-19 |
JPWO2017046948A1 (ja) | 2018-08-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6503458B2 (ja) | 薄膜トランジスタの製造方法及び表示パネル | |
KR100540947B1 (ko) | 표시장치와그제조방법 | |
US7387920B2 (en) | Method of manufacturing thin film transistor array panel | |
WO2017020358A1 (zh) | 低温多晶硅薄膜晶体管的制作方法及低温多晶硅薄膜晶体管 | |
JP6503459B2 (ja) | 半導体装置及びその製造方法 | |
JP2005072135A (ja) | 液晶表示装置及び薄膜トランジスタの製造方法 | |
JP2007298947A (ja) | 液晶表示装置及びその製造方法 | |
WO2015161596A1 (zh) | 多晶硅薄膜晶体管及其制备方法、阵列基板及其制备方法、显示装置 | |
JP2011033703A (ja) | 表示装置及びその製造方法 | |
JP2005228826A (ja) | 薄膜トランジスタとそれを用いた液晶表示装置およびその薄膜トランジスタの製造方法 | |
US6902961B2 (en) | Method of forming a CMOS thin film transistor device | |
KR100330165B1 (ko) | 박막 트랜지스터 액정 표시 장치의 제조 방법 | |
US10263121B2 (en) | Thin film transistor and method of manufacturing thin film transistor | |
JP2004200651A (ja) | トップゲート型薄膜トランジスタの形成方法 | |
JP6542897B2 (ja) | Ltps tft画素ユニット及びその製造方法 | |
JP2004014622A (ja) | 薄膜半導体装置の製造方法及びそのレジストパターン形成方法 | |
JP6480593B2 (ja) | 薄膜トランジスタの製造方法及び薄膜トランジスタ | |
JPH07211912A (ja) | 薄膜トランジスタ及びその製造方法 | |
US20130078787A1 (en) | Method for manufacturing semiconductor device | |
US8441051B2 (en) | Semiconductor device and manufacturing method thereof | |
US11081507B2 (en) | Semiconductor device and method for manufacturing same | |
KR20070109195A (ko) | 박막 트랜지스터 표시판 및 그 제조 방법 | |
JP2005191212A (ja) | 半導体装置及びその作製方法 | |
CN110870077A (zh) | 半导体装置以及其制造方法 | |
JP2010113151A (ja) | 表示装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180316 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180316 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190115 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190207 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6480593 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
LAPS | Cancellation because of no payment of annual fees |