JP6464762B2 - 半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法 - Google Patents

半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法 Download PDF

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JP6464762B2
JP6464762B2 JP2015006564A JP2015006564A JP6464762B2 JP 6464762 B2 JP6464762 B2 JP 6464762B2 JP 2015006564 A JP2015006564 A JP 2015006564A JP 2015006564 A JP2015006564 A JP 2015006564A JP 6464762 B2 JP6464762 B2 JP 6464762B2
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semiconductor package
underfill
package substrate
semiconductor chip
semiconductor
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Japanese (ja)
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JP2016134417A5 (enExample
JP2016134417A (ja
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石井　智之
智之 石井
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Toppan Inc
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Toppan Inc
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Priority to JP2015006564A priority Critical patent/JP6464762B2/ja
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

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  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
JP2015006564A 2015-01-16 2015-01-16 半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法 Active JP6464762B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2015006564A JP6464762B2 (ja) 2015-01-16 2015-01-16 半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2015006564A JP6464762B2 (ja) 2015-01-16 2015-01-16 半導体パッケージ基板、および半導体パッケージと、半導体パッケージ基板の製造方法、および半導体パッケージの製造方法

Publications (3)

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JP2016134417A JP2016134417A (ja) 2016-07-25
JP2016134417A5 JP2016134417A5 (enExample) 2018-02-01
JP6464762B2 true JP6464762B2 (ja) 2019-02-06

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020191397A (ja) * 2019-05-23 2020-11-26 凸版印刷株式会社 複合配線基板及びその製造方法
CN112992691B (zh) * 2021-04-23 2021-09-03 度亘激光技术（苏州）有限公司 半导体器件的焊接方法及半导体器件

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001244384A (ja) * 2000-02-28 2001-09-07 Matsushita Electric Works Ltd ベアチップ搭載プリント配線基板
JP4321269B2 (ja) * 2004-01-14 2009-08-26 株式会社デンソー 半導体装置
JP5162226B2 (ja) * 2007-12-12 2013-03-13 新光電気工業株式会社 配線基板及び半導体装置

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