JP6420671B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP6420671B2 JP6420671B2 JP2015009253A JP2015009253A JP6420671B2 JP 6420671 B2 JP6420671 B2 JP 6420671B2 JP 2015009253 A JP2015009253 A JP 2015009253A JP 2015009253 A JP2015009253 A JP 2015009253A JP 6420671 B2 JP6420671 B2 JP 6420671B2
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- lower mold
- mold cavity
- cavity block
- block
- semiconductor device
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Description
本実施の形態による半導体装置の製造方法がより明確となると思われるため、本発明者によって見出された、半導体チップを樹脂封止するモールド工程における課題について詳細に説明する。
1.半導体装置の構造
本実施の形態による半導体装置は、パッケージ基板上に半導体チップが搭載された樹脂封止型の半導体パッケージである。以下に、本実施の形態による半導体装置の一例としてBGAパッケージを取り上げて、その構造について図1を用いて説明する。図1は、半導体装置(BGAパッケージ)を示す要部断面図である。
パッケージ基板PSは、その厚さ方向と交差する平面形状が四角形になっている。パッケージ基板PSは多層配線構造からなり、本実施の形態では4つの配線層を有している。パッケージ基板PSの厚さは、例えば0.2〜0.6mm程度である。
半導体チップSCは、その厚さ方向と交差する平面形状が四角形になっており、例えばシリコンからなる半導体基板と、この半導体基板の主面(表面)に形成された複数の半導体素子と、絶縁層と配線層とをそれぞれ複数段積み重ねた多層配線層と、この多層配線層を覆うようにして形成された表面保護膜とを有する構成になっている。
パッケージ基板PSの下面PSyに形成された複数のバンプ・ランドBLには、複数の半田ボールSBが接合されている。複数のバンプ・ランドBLは、パッケージ基板PSの下面PSy側を被覆する保護膜PF2にそれぞれのバンプ・ランドBLに対応して形成された開口部により露出しており、複数の半田ボールSBは、複数のバンプ・ランドBLとそれぞれ電気的に、かつ機械的に接続されている。半田ボールSBとしては、鉛を実質的に含まない鉛フリー半田組成の半田バンプ、例えばSn−3[wt%]Ag−0.5[wt%]Cu組成の半田バンプなどが用いられる。
本実施の形態によるモールディング装置(モールド装置)の構造を図2(a)および(b)並びに図3を用いて説明する。図2(a)および(b)はそれぞれ、モールディング装置の一例を示す要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。図3は、下型キャビティブロックを搭載した下型ユニットを示す要部上面図である。
本実施の形態による半導体装置の製造方法(主としてモールド工程)について図4〜図13を用いて説明する。図4は、半導体装置の製造方法のモールド工程における工程図である。図5、図7、図8、図10並びに図12の各々の(a)および(b)はそれぞれ、モールド工程におけるモールディング装置の状態を説明する要部断面図およびモールディング装置の下型ユニットの一部を拡大して示す要部断面図である。図6、図9および図11は、モールド工程におけるモールディング装置の状態を説明する、モールド金型の上金型を透視した要部上面図である。図13は、モールド工程におけるモールディング装置の状態を説明する要部断面図である。
半導体ウエハの回路形成面に集積回路を形成する。集積回路は前工程または拡散工程と呼ばれる製造工程において、所定の製造プロセスに従って半導体ウエハにチップ単位で形成される。続いて、半導体ウエハに形成された各半導体チップの良・不良を判定した後、半導体ウエハをダイシングして、各半導体チップに個片化する。
上面と、上面とは反対側の下面とを有し、多層配線構造のパッケージ基板を準備する。例えばパッケージ基板は、長手方向に半導体製品1つ分に該当するチップ搭載領域が3つ配置される構成となっている(後述の図6参照)。
次に、パッケージ基板の上面(主面、表面)の各チップ搭載領域に、ダイボンド材(接着剤)を介して半導体チップを接合する。
次に、例えば熱圧着に超音波振動を併用したネイルヘッドボンディング法により、半導体チップの主面に形成された複数の電極パッドとパッケージ基板の上面に配置されたボンディング電極とを導電性部材(ボンディングワイヤ)を介してそれぞれ電気的に接続する(後述の図6参照)。ボンディングワイヤには、例えば15〜20μmφの金線を用いる。
≪ステップ1:基材(以下、参照。)の装着≫
まず、図5(a)および(b)並びに図6に示すように、下型キャビティブロックCVaの表面上に、被封止物である複数の半導体チップSCが搭載されたパッケージ基板PS(以下、基材STという。)を位置決めして、載置する。次に、下金型DMの温度を、例えば175℃程度に設定したまま、基材STに対して20秒程度のプレヒート処置を施す。この処理は、熱による基材STの変形を落ち着かせるなどの目的のために行われる。次に、下金型DMおよび上金型UMの温度を、例えば175℃程度に設定した状態で、基材STと下型キャビティCAVaの表面とを密着させる。
次に、図7(a)および(b)に示すように、下型ユニットDMU全体を型締め位置まで上方に移動(上昇)させる。そして、基材STのうち、半導体チップSCが搭載されておらず、かつ、導電性部材BWが接続されていないパッケージ基板PSの外周部の上面と、上金型UMの上型キャビティブロックCVbとを接触させて、上金型UMと下金型DMとを型締めする。これにより、上金型UMと下金型DMとの間にモールド樹脂が漏れることのないように隙間なくパッケージ基板PSを挟み、基材STを固定する。この時、型締め力(クランプ力、クランプ圧)により圧縮バネCSが圧縮されて、適正な圧力を維持したまま、下型ユニットDMUに対して下型キャビティブロックCVaおよび基材STが適切な位置まで下方に移動(下降)する。下型キャビティブロックCVaは、パッケージ基板PSの厚さ分、下方に移動する。
次に、上型キャビティCAVb内にモールド樹脂を注入する際の圧力または上型キャビティCAVb内に注入されたモールド樹脂に加える圧力などによって下型キャビティブロックCVaが下方に移動(下降)しないように、下型キャビティブロックCVaを固定する。
次に、図8(a)および(b)並びに図9に示すように、プランジャPLを上昇させてタブレットを押圧し、タブレットが溶融し、液体化したモールド樹脂MTAをポットPOから加圧移動させる。そして、下型キャビティブロックCVaを固定した状態で、カルブロックCBからランナRAおよびゲートGAを介して上型キャビティCAVb内へモールド樹脂MTAを注入する。
次に、図12(a)および(b)に示すように、所定時間経過後、モールド樹脂MTAが硬化して樹脂封止体RSが形成されたところで、下型ユニットDMU全体を型締め位置から下降させることにより、上金型UMと下型ユニットDMUとを開く。
次に、図13に示すように、複数のエジェクトピンEJPを上昇させて、複数のイジェクタピンEJPの一端側を下型キャビティブロックCVaの表面から突き出す。さらに、複数のエジェクトピンEJPを上昇させて、下型キャビティブロックCVaに装着された被封止物である基材(複数の半導体チップSCを樹脂封止したパッケージ基板PS)STを上方へ押し上げて、下型キャビティブロックCVaから基材(複数の半導体チップSCを樹脂封止したパッケージ基板PS)STを引き離す。
次に、下型キャビティブロックCVaから引き離された基材STをモールド金型から取り出す。その後、下型ユニットDMU全体を基材STの取り出し位置から上昇させることにより、モールド金型を初期の状態に戻す。
次に、パッケージ基板PSの上面側に複数の半導体チップSCを内包する一体的な樹脂封止体RSをモールディング装置から取り出し、切断工程において個々の半導体装置(BGAパッケージ)に切り分ける。その後、仕上がった半導体装置は製品規格によって選別され、検査工程を経た後、良品と判断された半導体装置は出荷される。
本実施の形態の変形例を図14および図15を用いて説明する。図14は、モールディング装置の変形例を示す要部断面図である。図15は、モールド工程におけるモールディング装置の変形例の状態を説明する、下型ユニットの一部を拡大して示す要部断面図である。
BE ボンディング電極
BL バンプ・ランド(電極パッド)
BW 導電性部材(ボンディングワイヤ)
CAVa 下型キャビティ
CAVb 上型キャビティ
CB カルブロック
CH 接続孔
CL1,CL2,CL3,CL4 配線層
CM 導電性部材
CO コア材
CS 圧縮バネ
CVa 下型キャビティブロック
CVb 上型キャビティブロック
DM 下金型(第1金型)
DMU 下型ユニット
EJP エジェクトピン
EP 電極パッド
GA ゲート
IL1,IL2 絶縁層
MB1,MB2,MB3,MB4 樹脂バリ
MTA モールド樹脂
PB ポットブロック
PF1,PF2 保護膜
PL プランジャ
PO ポット
PS パッケージ基板(基板、配線基板)
PSx 上面(表面)
PSy 下面(裏面)
RA ランナ
RS 樹脂封止体(封止体)
SB 半田ボール(外部端子)
SC 半導体チップ
SD 半導体装置(BGAパッケージ)
ST 基材
TH 貫通孔(ビア)
UM 上金型(第2金型)
UP 押し上げピン
UPH 押し上げピン用の孔
Claims (10)
- 以下の工程を含む半導体装置の製造方法:
(a)上型キャビティブロックを備える上金型と、下型キャビティブロックおよび押し上げピンを備える下金型と、樹脂を供給するポットを備えるポットブロックとを有するモールド金型を準備する工程;
(b)基板の上面に搭載された半導体チップを準備する工程;
(c)前記基板を前記下型キャビティブロックの表面上に配置する工程;
(d)前記上型キャビティブロックの上型キャビティ内に前記半導体チップが位置するように、前記上金型と前記下金型とで前記基板を挟む工程;
(e)前記ポットブロックの前記ポットから前記上型キャビティ内に前記樹脂を供給して、前記半導体チップを樹脂封止する工程;
(f)前記押し上げピンを前記下型キャビティブロックの前記表面とは反対側の裏面に押し当てて、前記(d)工程で沈み込んだ前記下型キャビティブロックを初期位置に戻す工程;
ここで、前記押し上げピンの先端面、および前記下型キャビティブロックの前記裏面のうち前記押し上げピンの前記先端面が接触する面は、前記ポット側に向かうに従って、前記下型キャビティブロックの前記表面との距離が長くなるように、傾斜している。 - 請求項1記載の半導体装置の製造方法において、
前記押し上げピンの先端面は、鏡面仕上げされている、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記押し上げピンの先端面の表面粗さは、十点平均粗さで3μm以下である、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記押し上げピンの先端面に、めっき処理が施されている、半導体装置の製造方法。 - 請求項4記載の半導体装置の製造方法において、
前記押し上げピンの先端面に、硬質クロムメッキが施されている、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
2以上の前記押し上げピンを前記下型キャビティブロックの前記裏面に押し当てる、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記下型キャビティブロックの初期位置では、前記下型キャビティブロックの前記表面と前記ポットブロックの上面とが同一平面となる、半導体装置の製造方法。 - 以下の工程を含む半導体装置の製造方法:
(a)上型キャビティブロックを備える上金型と、下型キャビティブロックおよび押し上げピンを備える下金型と、樹脂を供給するポットを備えるポットブロックとを有するモールド金型を準備する工程;
(b)基板の上面に搭載された半導体チップを準備する工程;
(c)前記基板を前記下型キャビティブロックの表面上に配置する工程;
(d)前記上型キャビティブロックの上型キャビティ内に前記半導体チップが位置するように、前記上金型と前記下金型とで前記基板を挟む工程;
(e)前記ポットブロックの前記ポットから前記上型キャビティ内に前記樹脂を供給して、前記半導体チップを樹脂封止する工程;
(f)前記押し上げピンを前記下型キャビティブロックの前記表面とは反対側の裏面に形成された孔に挿入し、前記孔の内壁に押し当てて、前記(d)工程で沈み込んだ前記下型キャビティブロックを初期位置に戻す工程;
ここで、前記押し上げピンが挿入される前記孔の側面の一部は、前記下型キャビティブロックの前記裏面側から前記表面側へ向かうに従って、前記孔の径が小さくなる方向に、傾斜している。 - 請求項8記載の半導体装置の製造方法において、
2以上の前記押し上げピンを前記下型キャビティブロックに形成された2以上の前記孔にそれぞれ挿入する、半導体装置の製造方法。 - 請求項8記載の半導体装置の製造方法において、
前記下型キャビティブロックの初期位置では、前記下型キャビティブロックの前記表面と前記ポットブロックの上面とが同一平面となる、半導体装置の製造方法。
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