JP6385677B2 - 基板加工方法 - Google Patents

基板加工方法 Download PDF

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Publication number
JP6385677B2
JP6385677B2 JP2014007690A JP2014007690A JP6385677B2 JP 6385677 B2 JP6385677 B2 JP 6385677B2 JP 2014007690 A JP2014007690 A JP 2014007690A JP 2014007690 A JP2014007690 A JP 2014007690A JP 6385677 B2 JP6385677 B2 JP 6385677B2
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Prior art keywords
substrate
film
carrier
thermosetting
adhesive film
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Japanese (ja)
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JP2014146793A5 (enExample
JP2014146793A (ja
Inventor
忠 善 李
忠 善 李
晶 ▲カン▼ 金
晶 ▲カン▼ 金
光 ▲チュル▼ 崔
光 ▲チュル▼ 崔
芸 ▲ビョン▼ 姜
芸 ▲ビョン▼ 姜
全 一 李
全 一 李
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Adhesives Or Adhesive Processes (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
  • Chemical Vapour Deposition (AREA)
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Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9064686B2 (en) 2010-04-15 2015-06-23 Suss Microtec Lithography, Gmbh Method and apparatus for temporary bonding of ultra thin wafers
KR20120082165A (ko) * 2011-01-13 2012-07-23 삼성전기주식회사 그린 시트 및 이의 제조방법
KR102046534B1 (ko) * 2013-01-25 2019-11-19 삼성전자주식회사 기판 가공 방법
JP6023737B2 (ja) * 2014-03-18 2016-11-09 信越化学工業株式会社 ウエハ加工体、ウエハ加工用仮接着材、及び薄型ウエハの製造方法
US10157766B2 (en) 2014-03-19 2018-12-18 Samsung Electronics Co., Ltd. Method of fabricating a semiconductor device
JP6193813B2 (ja) * 2014-06-10 2017-09-06 信越化学工業株式会社 ウエハ加工用仮接着材料、ウエハ加工体及びこれらを使用する薄型ウエハの製造方法
DE102015000451A1 (de) * 2015-01-15 2016-07-21 Siltectra Gmbh Unebener Wafer und Verfahren zum Herstellen eines unebenen Wafers
US10894935B2 (en) 2015-12-04 2021-01-19 Samsung Electronics Co., Ltd. Composition for removing silicone resins and method of thinning substrate by using the same
PL4296340T3 (pl) 2016-02-18 2025-08-04 Ecolab Usa Inc. Zastosowanie rozpuszczalnika podczas mycia butelek z wykorzystaniem preparatów na bazie amidyny
JP6691504B2 (ja) * 2016-05-12 2020-04-28 信越化学工業株式会社 ウエハ加工体及びその製造方法並びにウエハ上における有機膜の被覆性確認方法
EP3477685A4 (en) * 2016-06-22 2020-07-01 Nissan Chemical Corporation POLYDIMETHYLSILOXANE ADHESIVE
WO2018125673A2 (en) * 2016-12-28 2018-07-05 Invensas Bonding Technologies, Inc Processing stacked substrates
JP7262468B2 (ja) * 2017-12-29 2023-04-21 スリーエム イノベイティブ プロパティズ カンパニー 熱硬化性２剤型加工用接着剤組成物
US10964664B2 (en) 2018-04-20 2021-03-30 Invensas Bonding Technologies, Inc. DBI to Si bonding for simplified handle wafer
JP7424969B2 (ja) * 2018-05-01 2024-01-30 日産化学株式会社 耐熱性重合禁止剤を含むポリシロキサンを含有する仮接着剤
CN112602174B (zh) 2018-10-16 2023-12-08 株式会社力森诺科 组合物、粘接性聚合物的清洗方法、器件晶圆的制造方法和支撑晶圆的再生方法
JP7759027B2 (ja) * 2020-08-27 2025-10-23 日産化学株式会社 積層体及び剥離剤組成物
TW202303826A (zh) * 2021-02-15 2023-01-16 美商布魯爾科技公司 防止熱壓結合中金屬連接變形的臨時結合和脫結製程

Family Cites Families (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5863832A (en) 1996-06-28 1999-01-26 Intel Corporation Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system
US6230569B1 (en) 1999-05-24 2001-05-15 Micron Technology, Inc. Use of a stream of compressed gas to detect semiconductor interconnect problems
JP4137310B2 (ja) * 1999-09-06 2008-08-20 リンテック株式会社 両面粘着シートに固定された物品の剥離方法および剥離装置
US20030107927A1 (en) 2001-03-12 2003-06-12 Yeda Research And Development Co. Ltd. Method using a synthetic molecular spring device in a system for dynamically controlling a system property and a corresponding system thereof
US7534498B2 (en) * 2002-06-03 2009-05-19 3M Innovative Properties Company Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body
JP3832408B2 (ja) 2002-09-11 2006-10-11 松下電器産業株式会社 半導体装置の製造方法
US20040265531A1 (en) 2003-06-30 2004-12-30 Mckean Dennis R. Sliders bonded by a debondable silicon-based encapsulant
US20050066995A1 (en) * 2003-09-30 2005-03-31 International Business Machines Corporation Non-hermetic encapsulant removal for module rework
US20070134846A1 (en) 2003-10-07 2007-06-14 Nagase & Co. Ltd. Electronic member fabricating method and ic chip with adhesive material
JP2005129653A (ja) 2003-10-22 2005-05-19 Fuji Electric Holdings Co Ltd 半導体装置の製造方法
US7226812B2 (en) * 2004-03-31 2007-06-05 Intel Corporation Wafer support and release in wafer processing
US7196872B2 (en) 2004-04-29 2007-03-27 Hitachi Global Storage Netherlands, B.V. Sliders bonded by a debondable encapsulant comprising different polymers formed via in situ polymerization
JP4613709B2 (ja) 2005-06-24 2011-01-19 セイコーエプソン株式会社 半導体装置の製造方法
CN101536172B (zh) 2006-10-30 2012-05-30 住友电木株式会社 液体树脂组合物、具粘合剂层的半导体晶片、具粘合剂层的半导体元件、封装件及其制法
JP5196838B2 (ja) * 2007-04-17 2013-05-15 リンテック株式会社 接着剤付きチップの製造方法
DE102007020655A1 (de) * 2007-04-30 2008-11-06 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Verfahren zum Herstellen dünner Schichten und entsprechende Schicht
US20080302481A1 (en) 2007-06-07 2008-12-11 Tru-Si Technologies, Inc. Method and apparatus for debonding of structures which are bonded together, including (but not limited to) debonding of semiconductor wafers from carriers when the bonding is effected by double-sided adhesive tape
JP2009141070A (ja) * 2007-12-05 2009-06-25 Lintec Corp 剥離装置及び剥離方法
JP2009209345A (ja) 2008-02-06 2009-09-17 Hitachi Chem Co Ltd 粘接着シート
US8092628B2 (en) 2008-10-31 2012-01-10 Brewer Science Inc. Cyclic olefin compositions for temporary wafer bonding
WO2010121068A2 (en) 2009-04-16 2010-10-21 Suss Microtec, Inc. Improved apparatus for temporary wafer bonding and debonding
US8871609B2 (en) 2009-06-30 2014-10-28 Taiwan Semiconductor Manufacturing Company, Ltd. Thin wafer handling structure and method
US8236118B2 (en) 2009-08-07 2012-08-07 Guardian Industries Corp. Debonding and transfer techniques for hetero-epitaxially grown graphene, and products including the same
US9847243B2 (en) 2009-08-27 2017-12-19 Corning Incorporated Debonding a glass substrate from carrier using ultrasonic wave
US8398804B2 (en) 2010-01-11 2013-03-19 Navaid Baqai Pressure sensitive textile adhesive
US8017439B2 (en) 2010-01-26 2011-09-13 Texas Instruments Incorporated Dual carrier for joining IC die or wafers to TSV wafers
US8852391B2 (en) 2010-06-21 2014-10-07 Brewer Science Inc. Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate
JP5583080B2 (ja) 2010-07-07 2014-09-03 古河電気工業株式会社 ウエハ加工用テープおよびそれを用いた半導体加工方法
US9263314B2 (en) 2010-08-06 2016-02-16 Brewer Science Inc. Multiple bonding layers for thin-wafer handling
FR2964048B1 (fr) * 2010-08-30 2012-09-21 Commissariat Energie Atomique Procédé de réalisation d'un film, par exemple monocristallin, sur un support en polymère
US8313982B2 (en) 2010-09-20 2012-11-20 Texas Instruments Incorporated Stacked die assemblies including TSV die
US9029269B2 (en) * 2011-02-28 2015-05-12 Dow Corning Corporation Wafer bonding system and method for bonding and debonding thereof
KR20130000211A (ko) * 2011-06-22 2013-01-02 삼성전자주식회사 기판 가공 방법

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US9595446B2 (en) 2017-03-14

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