JP2014146793A - 基板加工方法 - Google Patents
基板加工方法 Download PDFInfo
- Publication number
- JP2014146793A JP2014146793A JP2014007690A JP2014007690A JP2014146793A JP 2014146793 A JP2014146793 A JP 2014146793A JP 2014007690 A JP2014007690 A JP 2014007690A JP 2014007690 A JP2014007690 A JP 2014007690A JP 2014146793 A JP2014146793 A JP 2014146793A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- film
- carrier
- release film
- processing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 176
- 238000000034 method Methods 0.000 title abstract description 27
- 229920001187 thermosetting polymer Polymers 0.000 claims abstract description 49
- 239000002313 adhesive film Substances 0.000 claims description 120
- 238000003672 processing method Methods 0.000 claims description 59
- UQEAIHBTYFGYIE-UHFFFAOYSA-N hexamethyldisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)C UQEAIHBTYFGYIE-UHFFFAOYSA-N 0.000 claims description 37
- 239000000463 material Substances 0.000 claims description 36
- 239000002243 precursor Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims description 30
- 239000004205 dimethyl polysiloxane Substances 0.000 claims description 19
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 claims description 19
- 238000004140 cleaning Methods 0.000 claims description 13
- 238000005229 chemical vapour deposition Methods 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 12
- FPGGTKZVZWFYPV-UHFFFAOYSA-M tetrabutylammonium fluoride Chemical compound [F-].CCCC[N+](CCCC)(CCCC)CCCC FPGGTKZVZWFYPV-UHFFFAOYSA-M 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- KPUWHANPEXNPJT-UHFFFAOYSA-N disiloxane Chemical class [SiH3]O[SiH3] KPUWHANPEXNPJT-UHFFFAOYSA-N 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000000126 substance Substances 0.000 claims description 9
- -1 polydimethylsiloxane Polymers 0.000 claims description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 6
- 239000012528 membrane Substances 0.000 claims description 6
- 238000009832 plasma treatment Methods 0.000 claims description 5
- 239000007788 liquid Substances 0.000 claims description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-M Acetate Chemical compound CC([O-])=O QTBSBXVTEAMEQO-UHFFFAOYSA-M 0.000 claims description 3
- 229910052786 argon Inorganic materials 0.000 claims description 3
- 239000011521 glass Substances 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- AFFLGGQVNFXPEV-UHFFFAOYSA-N n-decene Natural products CCCCCCCCC=C AFFLGGQVNFXPEV-UHFFFAOYSA-N 0.000 claims description 2
- 230000001902 propagating effect Effects 0.000 claims description 2
- 239000012495 reaction gas Substances 0.000 claims description 2
- 238000005728 strengthening Methods 0.000 claims description 2
- 239000003292 glue Substances 0.000 abstract 2
- 235000012431 wafers Nutrition 0.000 description 100
- 239000010410 layer Substances 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- 239000010703 silicon Substances 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 7
- 230000001070 adhesive effect Effects 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 7
- 238000005520 cutting process Methods 0.000 description 6
- 230000010365 information processing Effects 0.000 description 6
- 238000005096 rolling process Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000000644 propagated effect Effects 0.000 description 5
- 238000004528 spin coating Methods 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000000059 patterning Methods 0.000 description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 4
- 238000005411 Van der Waals force Methods 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- 239000003999 initiator Substances 0.000 description 3
- 238000002156 mixing Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 239000012071 phase Substances 0.000 description 3
- 230000001681 protective effect Effects 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000002904 solvent Substances 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- IRIIKYVSZMJVNX-UHFFFAOYSA-N 2,4,6-tris(2-methylaziridin-1-yl)-1,3,5-triazine Chemical compound CC1CN1C1=NC(N2C(C2)C)=NC(N2C(C2)C)=N1 IRIIKYVSZMJVNX-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920006336 epoxy molding compound Polymers 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000007791 liquid phase Substances 0.000 description 2
- 238000000053 physical method Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- 239000007921 spray Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000009281 ultraviolet germicidal irradiation Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68318—Auxiliary support including means facilitating the separation of a device or wafer from the auxiliary support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/03001—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
- H01L2224/03002—Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate for supporting the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/036—Manufacturing methods by patterning a pre-deposited material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92222—Sequential connecting processes the first connecting process involving a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/03—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Adhesives Or Adhesive Processes (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Chemical Vapour Deposition (AREA)
Abstract
【解決手段】本発明による基板加工方法は、基板とキャリヤとの間に結合膜を提供して前記基板を前記キャリヤに結合し、前記基板が前記キャリヤによって支持された状態で前記基板を加工し、そして前記結合膜を除去して前記基板を前記キャリヤから分離することを包含することができる。前記結合膜は、熱硬化性接着膜と前記熱硬化性接着膜の両面に提供された熱硬化性剥離膜とを包含することができる。
【選択図】 図1I
Description
本発明の他の目的はキャリヤを基板から容易に分離できる基板加工方法を提供することである。
一実施形態の方法において、前記熱硬化性剥離膜は、前記熱硬化性接着膜と前記基板との間に提供された第1剥離膜と、前記熱硬化性接着膜と前記キャリヤとの間に提供された第2剥離膜と、を包含することができる。
一実施形態の方法において、前記結合膜を提供することは、前記第1及び第2剥離膜と前記接着膜とを硬化させることをさらに含むことができる。
一実施形態の方法において、前記接着膜をプラズマ処理することは、酸素、窒素、アルゴンの中で少なくともいずれか1つを含むプラズマによって前記第2剥離膜の残留物を前記接着膜から除去することを包含することができる。
前記接着膜は、前記基板及び前記キャリヤの露出された縁と接触することができる。
他の実施形態の方法において、前記第1剥離膜と前記第2剥離膜との中で少なくともいずれか1つは、ポリジメチルシロキサン(PDMS)とヘキサメチルジシロキサン(HMDSO)との中で少なくともいずれか1つを包含することができる。前記接着膜は、シロキサン(siloxane)を包含することができる。
他の実施形態の方法において、前記第1剥離膜を除去することは、前記薄形化された基板を洗浄することを包含することができる。
その他の実施形態の方法において、前記結合膜を提供することは、前記結合膜を熱に露出させて前記結合膜を強化させることを包含することができる。
その他の実施形態の方法において、前記結合膜は、接着膜と、前記基板の前記第1面と前記接着膜に結合される第1剥離膜と、前記キャリヤの前記第1面と前記接着膜に結合される第2剥離膜と、を包含することができる。
その他の実施形態の方法において、前記接着膜は、前記基板の縁と前記キャリヤの縁との中で少なくともいずれか1つに直接的に結合され得る。
本発明と従来技術とを比較した長所は添付された図面を参照した詳細な説明と特許請求の範囲を通じて明確になり得る。特に、本発明は特許請求の範囲で明確に請求される。しかし、本発明は添付された図面に関連して次の詳細な説明を参照することによって最も良く理解することができる。図面において、同一の参照符号は多様な図面を通じて同一の構成要素を示す。
図1A乃至図1Pは本発明の一実施形態による基板加工方法を示した断面図である。図1C、図1E及び図1Iは図1B、図1D及び図1Hの一部を各々示した断面図である。図1F及び図1Gは図1Bの変形形態を示した断面図である。
接着膜250は第1剥離膜210上に前記化学式を有するシリコン(silicone)或いはこれを含む熱硬化性樹脂(resin)をコーティングして形成することができる。一例として、接着膜250はシロキサン(siloxane)系列の物質で形成することができる。他の例として、接着膜250はトリプロピレンメラミン(TMAT:tripropylenemelamine)或いはこれを含む物質で形成することができる。
第1剥離膜210の厚さTr1が厚いほど、接着膜250をウエハ100から分離するのに必要である力は低くなり得る。第1剥離膜210の厚さTr1は第1前駆体膜211の厚さTp1及び/又はプラズマ化学気相蒸着条件によって異なり得る。
プラズマ強度が強いほど、プラズマ時間が長いほど、第1剥離膜210は硬く(hard)なり得る。これと異なり、プラズマ強度が弱いほど、プラズマ時間が短いほど、第1剥離膜210は軟らか(soft)になり得る。第1剥離膜210があまりにも硬くなれば、第1剥離膜210の自己剥離(self−delamination)やクラック(crack)が生じる恐れがあり、あまりにも軟らかになれば、第1剥離膜210が液相状態に留まって容易に剥がれてしまう。前述のプラズマ蒸着条件によれば、完全架橋結合された(fully cross−linked)或いはこれと類似な構造を有する安定的な第1剥離膜210が形成され得る。
図1Qは本発明の一実施形態による基板加工方法を利用する半導体チップの製造方法を示した断面図である。図1Rは本発明の一実施形態による基板加工方法を利用する半導体パッケージの製造方法を示した断面図である。
図1Qを参照すれば、ウエハ100を複数個の半導体チップ10に分離することができる。カッティングホィール800によってウエハ100のスクライブレーンを切断することによってウエハ100を複数個の半導体チップ10に分離するウエハ切断(wafer sawing)工程を進行することができる。このようにウエハ100から分離された複数個の半導体チップ10の中で少なくとも1つをパッケージングすることができる。他の例として、レーザ或いはその他のカッティング器具を利用して前記ウエハ切断工程を進行することができる。
図2A乃至図2Fは本発明の他の実施形態による基板加工方法を示した断面図である。図2Dは図2Cの一部を拡大示した断面図である。
図2Aを参照すれば、ウエハ100の活性面100a上に第1剥離膜210と接着膜250とを形成することができる。例えば、ウエハ100の活性面100a上に熱硬化性物質をスピンコーティングし、プラズマ化学気相蒸着した後、パターニングして第1剥離膜210を形成することができる。前記パターニングによって第1剥離膜210はウエハ100の縁100eを露出させ得る。接着膜250は第1剥離膜210上に形成され、ウエハ100の縁100eと結合され得る。
他の例として、図1Fのように接着膜250はキャリヤ300上に形成され得る。その他の例として、図1Gのようにウエハ100とキャリヤ300との上に第1接着膜250aと第2接着膜250bとが各々形成され得る。
図3Aは本発明の実施形態による基板加工方法を通じて得られた半導体装置を具備するメモリカードを示したブロック図である。図3Bは本発明の実施形態による基板加工方法を通じて得られた半導体装置を応用した情報処理システムを示したブロック図である。
100・・・基板
105・・・集積回路
111・・・貫通電極
113・・・バンプ
200・・・結合膜
210・・・第1剥離膜
220・・・第2剥離膜
250・・・接着膜
300・・・キャリヤ
400・・・イニシエータ
500・・・保護テープ
600・・・ローリングテープ
700・・・スプレ
800・・・カッティングホィール
900・・・印刷回路基板
910・・・モールド膜
920・・・外部端子
Claims (23)
- 基板とキャリヤとの間に熱硬化性接着膜と前記熱硬化性接着膜との両面上に提供された熱硬化性剥離膜を含む結合膜を提供して前記基板と前記キャリヤとを結合し、
前記キャリヤによって前記基板が支持された状態で前記基板を加工し、
前記結合膜を除去して前記基板を前記キャリヤから分離することを含む基板加工方法。 - 前記基板と前記結合膜との間の結合力は前記キャリヤと前記結合膜との間の結合力に比べて大きい請求項1に記載の基板加工方法。
- 前記熱硬化性剥離膜は、
前記熱硬化性接着膜と前記基板との間に提供された第1剥離膜と、
前記熱硬化性接着膜と前記キャリヤとの間に提供された第2剥離膜と、を含む請求項1に記載の基板加工方法。 - 前記結合膜を提供することは、
前記基板上に第1熱硬化性物質を提供して前記第1剥離膜を形成し、
前記キャリヤ上に第2熱硬化性物質を提供して前記第2剥離膜を形成し、
前記基板及び前記キャリヤの中で少なくともいずれか1つの上に第3熱硬化性物質を提供して前記接着膜を形成することを含む請求項3に記載の基板加工方法。 - 前記第1剥離膜を形成することは、
ポリジメチルシロキサン(PDMS)とヘキサメチルジシロキサン(HMDSO)とを含む前駆体を前記基板上にコーティングして前駆体膜を形成し、
前記ヘキサメチルジシロキサン(HMDSO)を反応ガスとして使用した化学気相蒸着で前記前駆体膜上に蒸着膜を形成することを含む請求項4に記載の基板加工方法。 - 前記第2剥離膜を形成することは、
ポリジメチルシロキサン(PDMS)とヘキサメチルジシロキサン(HMDSO)とを含む前駆体を前記キャリヤ上にコーティングして前駆体膜を形成し、
前記ヘキサメチルジシロキサン(HMDSO)と酸素を反応ガスとして使用した化学気相蒸着で前記前駆体膜上に蒸着膜を形成することを含む請求項4に記載の基板加工方法。 - 前記接着膜を形成することは、
前記第1剥離膜と前記第2剥離膜との中で少なくとも1つ上にシロキサン(siloxane)或いは前記シロキサンを含む熱硬化性物質をコーティングすることを含む請求項4に記載の基板加工方法。 - 前記結合膜を提供することは、
前記第1及び第2剥離膜と前記接着膜を硬化させることをさらに含む請求項4に記載の基板加工方法。 - 前記基板を前記キャリヤから分離することは、
前記接着膜の縁にクラックを形成し、
前記キャリヤを前記接着膜から分離し、
前記接着膜をプラズマ処理し、
前記接着膜を前記基板から分離し、
前記基板を洗浄することを含む請求項3に記載の基板加工方法。 - 前記接着膜をプラズマ処理することは、
酸素、窒素、アルゴンの中で少なくともいずれか1つを含むプラズマで前記第2剥離膜の残留物を前記接着膜から除去することを含む請求項9に記載の基板加工方法。 - 前記基板を洗浄することは、
前記基板上に洗浄液を提供して前記基板から前記第1剥離膜の残留物を除去することを含み、
前記洗浄液はDBU(Diazabicycloundecene)及びテトラ−n−ブチルアンモニウムフルオライド(TBAF)の中で少なくともいずれか1つと混合されたアセテート(acetate)を含む請求項9に記載の基板加工方法。 - 前記結合膜を提供することは、
前記基板上に第1熱硬化性物質を提供して前記第1剥離膜を形成し、そして前記基板の縁を露出させ、
前記キャリヤ上に第2熱硬化性物質を提供して前記第2剥離膜を形成し、そして前記キャリヤの縁を露出させ、
前記基板及び前記キャリヤの中で少なくともいずれか1つ上に第3熱硬化性物質を提供して前記接着膜を形成することを含み、
前記接着膜は、前記基板及び前記キャリヤの露出された縁と接触する請求項3に記載の基板加工方法。 - 基板上に熱硬化性第1剥離膜を形成し、
キャリヤ上に熱硬化性第2剥離膜を形成し、
前記基板と前記キャリヤとの間に第1剥離膜及び前記第2剥離膜と接着される熱硬化性接着膜を提供して前記基板を前記キャリヤに結合し、
前記キャリヤによって支持された状態で前記基板を薄型化し、
前記キャリヤを前記基板から分離し、
前記接着膜をプラズマ処理して前記接着膜上の前記第2剥離膜を除去し、
前記接着膜を前記薄形化された基板から分離し、
前記薄形化された基板上の前記第1剥離膜を除去することを含む基板加工方法。 - 前記基板を薄型化することは、
前記基板の中で前記第1剥離膜が形成された第1面の反対面である第2面をリセスすることを含み、
前記薄形化された基板のリセスされた第2面を通じて前記基板に含まれた貫通電極が露出される請求項13に記載の基板加工方法。 - 前記第1剥離膜と前記第2剥離膜との中で少なくともいずれか1つは、ポリジメチルシロキサン(PDMS)とヘキサメチルジシロキサン(HMDSO)との中で少なくともいずれか1つを含み、前記接着膜は、シロキサン(siloxane)を含む請求項13に記載の基板加工方法。
- 前記基板は、複数個のバンプと前記バンプと電気的に連結された複数個の貫通電極を含む半導体ウエハであり、そして前記キャリヤは、前記基板と同一な物質或いはガラスを含む請求項13に記載の基板加工方法。
- 前記第1剥離膜を除去することは、前記薄形化された基板を洗浄することを含む請求項13に記載の基板加工方法。
- 基板の第1面とキャリヤの第1面とに結合され、前記基板との結合力が前記キャリヤとの結合力に比べて大きい結合膜を提供し、
前記結合膜が前記基板と結合され、前記キャリヤが前記結合膜に結合された状態で、前記基板の前記第1面の反対面である前記基板の第2面を加工し、
前記基板から前記結合膜を除去することを含む基板加工方法。 - 前記結合膜は、熱硬化性物質を含む請求項18に記載の基板加工方法。
- 前記結合膜を提供することは、
前記結合膜を熱に露出させて前記結合膜を強化させることを含む請求項19に記載の基板加工方法。 - 前記結合膜は、
接着膜と、
前記基板の前記第1面と前記接着膜に結合される第1剥離膜と、
前記キャリヤの前記第1面と前記接着膜に結合される第2剥離膜と、を含む請求項18に記載の基板加工方法。 - 前記結合膜を除去することは、
前記第2剥離膜にしたがってクラックを伝搬させて前記キャリヤを前記結合膜から分離し、
前記キャリヤが前記結合膜から分離された以後に前記第2剥離膜と前記接着膜との中で少なくともいずれか1つを前記基板から除去することを含む請求項21に記載の基板加工方法。 - 前記接着膜は、前記基板の縁と前記キャリヤの縁との中で少なくともいずれか1つに直接的に結合される請求項21に記載の基板加工方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020130008695A KR102077248B1 (ko) | 2013-01-25 | 2013-01-25 | 기판 가공 방법 |
KR10-2013-0008695 | 2013-01-25 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2014146793A true JP2014146793A (ja) | 2014-08-14 |
JP2014146793A5 JP2014146793A5 (ja) | 2017-03-30 |
JP6385677B2 JP6385677B2 (ja) | 2018-09-05 |
Family
ID=51223376
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014007690A Active JP6385677B2 (ja) | 2013-01-25 | 2014-01-20 | 基板加工方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US9595446B2 (ja) |
JP (1) | JP6385677B2 (ja) |
KR (1) | KR102077248B1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017221772A1 (ja) * | 2016-06-22 | 2017-12-28 | 日産化学工業株式会社 | ポリジメチルシロキサンを含有する接着剤 |
KR20210008519A (ko) | 2018-10-16 | 2021-01-22 | 쇼와 덴코 가부시키가이샤 | 조성물, 접착성 폴리머의 세정 방법, 디바이스 웨이퍼의 제조 방법, 및 지지 웨이퍼의 재생 방법 |
JP2021509135A (ja) * | 2017-12-29 | 2021-03-18 | スリーエム イノベイティブ プロパティズ カンパニー | 熱硬化性2剤型加工用接着剤組成物 |
WO2022045026A1 (ja) | 2020-08-27 | 2022-03-03 | 日産化学株式会社 | 積層体及び剥離剤組成物 |
KR102703576B1 (ko) | 2017-12-29 | 2024-09-04 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | 열경화성 2 파트 가공 접착제 조성물 |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9064686B2 (en) | 2010-04-15 | 2015-06-23 | Suss Microtec Lithography, Gmbh | Method and apparatus for temporary bonding of ultra thin wafers |
KR20120082165A (ko) * | 2011-01-13 | 2012-07-23 | 삼성전기주식회사 | 그린 시트 및 이의 제조방법 |
KR102046534B1 (ko) * | 2013-01-25 | 2019-11-19 | 삼성전자주식회사 | 기판 가공 방법 |
JP6023737B2 (ja) * | 2014-03-18 | 2016-11-09 | 信越化学工業株式会社 | ウエハ加工体、ウエハ加工用仮接着材、及び薄型ウエハの製造方法 |
US10157766B2 (en) | 2014-03-19 | 2018-12-18 | Samsung Electronics Co., Ltd. | Method of fabricating a semiconductor device |
JP6193813B2 (ja) * | 2014-06-10 | 2017-09-06 | 信越化学工業株式会社 | ウエハ加工用仮接着材料、ウエハ加工体及びこれらを使用する薄型ウエハの製造方法 |
DE102015000451A1 (de) * | 2015-01-15 | 2016-07-21 | Siltectra Gmbh | Unebener Wafer und Verfahren zum Herstellen eines unebenen Wafers |
US10894935B2 (en) | 2015-12-04 | 2021-01-19 | Samsung Electronics Co., Ltd. | Composition for removing silicone resins and method of thinning substrate by using the same |
AU2017221372B2 (en) | 2016-02-18 | 2019-04-18 | Ecolab Usa Inc. | Solvent application in bottle wash using amidine based formulas |
JP6691504B2 (ja) * | 2016-05-12 | 2020-04-28 | 信越化学工業株式会社 | ウエハ加工体及びその製造方法並びにウエハ上における有機膜の被覆性確認方法 |
CN110178212B (zh) * | 2016-12-28 | 2024-01-09 | 艾德亚半导体接合科技有限公司 | 堆栈基板的处理 |
US10964664B2 (en) | 2018-04-20 | 2021-03-30 | Invensas Bonding Technologies, Inc. | DBI to Si bonding for simplified handle wafer |
US20220262755A1 (en) * | 2021-02-15 | 2022-08-18 | Brewer Science, Inc. | Temporary bonding and debonding process to prevent deformation of metal connection in thermocompression bonding |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050221598A1 (en) * | 2004-03-31 | 2005-10-06 | Daoqiang Lu | Wafer support and release in wafer processing |
WO2012118700A1 (en) * | 2011-02-28 | 2012-09-07 | Dow Corning Corporation | Wafer bonding system and method for bonding and debonding thereof |
US20120329249A1 (en) * | 2011-06-22 | 2012-12-27 | Ahn Jung-Seok | Methods of processing substrates |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5863832A (en) | 1996-06-28 | 1999-01-26 | Intel Corporation | Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system |
US6230569B1 (en) | 1999-05-24 | 2001-05-15 | Micron Technology, Inc. | Use of a stream of compressed gas to detect semiconductor interconnect problems |
JP4137310B2 (ja) * | 1999-09-06 | 2008-08-20 | リンテック株式会社 | 両面粘着シートに固定された物品の剥離方法および剥離装置 |
US20030107927A1 (en) | 2001-03-12 | 2003-06-12 | Yeda Research And Development Co. Ltd. | Method using a synthetic molecular spring device in a system for dynamically controlling a system property and a corresponding system thereof |
US7534498B2 (en) * | 2002-06-03 | 2009-05-19 | 3M Innovative Properties Company | Laminate body, method, and apparatus for manufacturing ultrathin substrate using the laminate body |
JP3832408B2 (ja) | 2002-09-11 | 2006-10-11 | 松下電器産業株式会社 | 半導体装置の製造方法 |
US20040265531A1 (en) | 2003-06-30 | 2004-12-30 | Mckean Dennis R. | Sliders bonded by a debondable silicon-based encapsulant |
US20050066995A1 (en) * | 2003-09-30 | 2005-03-31 | International Business Machines Corporation | Non-hermetic encapsulant removal for module rework |
US20070134846A1 (en) | 2003-10-07 | 2007-06-14 | Nagase & Co. Ltd. | Electronic member fabricating method and ic chip with adhesive material |
JP2005129653A (ja) | 2003-10-22 | 2005-05-19 | Fuji Electric Holdings Co Ltd | 半導体装置の製造方法 |
US7196872B2 (en) | 2004-04-29 | 2007-03-27 | Hitachi Global Storage Netherlands, B.V. | Sliders bonded by a debondable encapsulant comprising different polymers formed via in situ polymerization |
JP4613709B2 (ja) * | 2005-06-24 | 2011-01-19 | セイコーエプソン株式会社 | 半導体装置の製造方法 |
MY148064A (en) | 2006-10-30 | 2013-02-28 | Sumitomo Bakelite Co | Liquid resin composition, semiconductor wafer having adhesive layer, semiconductor element having adhesive layer, semiconductor package , process for manufacturing semiconductor element and process for manufacturing semiconductor package. |
JP5196838B2 (ja) * | 2007-04-17 | 2013-05-15 | リンテック株式会社 | 接着剤付きチップの製造方法 |
DE102007020655A1 (de) * | 2007-04-30 | 2008-11-06 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Verfahren zum Herstellen dünner Schichten und entsprechende Schicht |
US20080302481A1 (en) * | 2007-06-07 | 2008-12-11 | Tru-Si Technologies, Inc. | Method and apparatus for debonding of structures which are bonded together, including (but not limited to) debonding of semiconductor wafers from carriers when the bonding is effected by double-sided adhesive tape |
JP2009141070A (ja) * | 2007-12-05 | 2009-06-25 | Lintec Corp | 剥離装置及び剥離方法 |
JP2009209345A (ja) | 2008-02-06 | 2009-09-17 | Hitachi Chem Co Ltd | 粘接着シート |
US8092628B2 (en) | 2008-10-31 | 2012-01-10 | Brewer Science Inc. | Cyclic olefin compositions for temporary wafer bonding |
US8919412B2 (en) | 2009-04-16 | 2014-12-30 | Suss Microtec Lithography, Gmbh | Apparatus for thermal-slide debonding of temporary bonded semiconductor wafers |
US8871609B2 (en) | 2009-06-30 | 2014-10-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Thin wafer handling structure and method |
US8236118B2 (en) | 2009-08-07 | 2012-08-07 | Guardian Industries Corp. | Debonding and transfer techniques for hetero-epitaxially grown graphene, and products including the same |
US9847243B2 (en) | 2009-08-27 | 2017-12-19 | Corning Incorporated | Debonding a glass substrate from carrier using ultrasonic wave |
US8398804B2 (en) | 2010-01-11 | 2013-03-19 | Navaid Baqai | Pressure sensitive textile adhesive |
US8017439B2 (en) | 2010-01-26 | 2011-09-13 | Texas Instruments Incorporated | Dual carrier for joining IC die or wafers to TSV wafers |
US8852391B2 (en) | 2010-06-21 | 2014-10-07 | Brewer Science Inc. | Method and apparatus for removing a reversibly mounted device wafer from a carrier substrate |
JP5583080B2 (ja) | 2010-07-07 | 2014-09-03 | 古河電気工業株式会社 | ウエハ加工用テープおよびそれを用いた半導体加工方法 |
US9263314B2 (en) | 2010-08-06 | 2016-02-16 | Brewer Science Inc. | Multiple bonding layers for thin-wafer handling |
FR2964048B1 (fr) * | 2010-08-30 | 2012-09-21 | Commissariat Energie Atomique | Procédé de réalisation d'un film, par exemple monocristallin, sur un support en polymère |
US8313982B2 (en) | 2010-09-20 | 2012-11-20 | Texas Instruments Incorporated | Stacked die assemblies including TSV die |
-
2013
- 2013-01-25 KR KR1020130008695A patent/KR102077248B1/ko active IP Right Grant
-
2014
- 2014-01-09 US US14/150,906 patent/US9595446B2/en active Active
- 2014-01-20 JP JP2014007690A patent/JP6385677B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050221598A1 (en) * | 2004-03-31 | 2005-10-06 | Daoqiang Lu | Wafer support and release in wafer processing |
WO2012118700A1 (en) * | 2011-02-28 | 2012-09-07 | Dow Corning Corporation | Wafer bonding system and method for bonding and debonding thereof |
JP2014514728A (ja) * | 2011-02-28 | 2014-06-19 | ダウ コーニング コーポレーション | ウェハ接着システム、及びその接着並びに剥離方法 |
US20120329249A1 (en) * | 2011-06-22 | 2012-12-27 | Ahn Jung-Seok | Methods of processing substrates |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2017221772A1 (ja) * | 2016-06-22 | 2017-12-28 | 日産化学工業株式会社 | ポリジメチルシロキサンを含有する接着剤 |
JPWO2017221772A1 (ja) * | 2016-06-22 | 2019-04-11 | 日産化学株式会社 | ポリジメチルシロキサンを含有する接着剤 |
US11183415B2 (en) | 2016-06-22 | 2021-11-23 | Nissan Chemical Corporation | Adhesive containing polydimethyl siloxane |
JP2021509135A (ja) * | 2017-12-29 | 2021-03-18 | スリーエム イノベイティブ プロパティズ カンパニー | 熱硬化性2剤型加工用接着剤組成物 |
JP7262468B2 (ja) | 2017-12-29 | 2023-04-21 | スリーエム イノベイティブ プロパティズ カンパニー | 熱硬化性2剤型加工用接着剤組成物 |
KR102703576B1 (ko) | 2017-12-29 | 2024-09-04 | 쓰리엠 이노베이티브 프로퍼티즈 컴파니 | 열경화성 2 파트 가공 접착제 조성물 |
KR20210008519A (ko) | 2018-10-16 | 2021-01-22 | 쇼와 덴코 가부시키가이샤 | 조성물, 접착성 폴리머의 세정 방법, 디바이스 웨이퍼의 제조 방법, 및 지지 웨이퍼의 재생 방법 |
US11807837B2 (en) | 2018-10-16 | 2023-11-07 | Resonac Corporation | Composition, method for cleaning adhesive polymer, method for producing device wafer, and method for regenerating support wafer |
WO2022045026A1 (ja) | 2020-08-27 | 2022-03-03 | 日産化学株式会社 | 積層体及び剥離剤組成物 |
KR20230058653A (ko) | 2020-08-27 | 2023-05-03 | 닛산 가가쿠 가부시키가이샤 | 적층체 및 박리제 조성물 |
Also Published As
Publication number | Publication date |
---|---|
KR102077248B1 (ko) | 2020-02-13 |
US9595446B2 (en) | 2017-03-14 |
US20140213039A1 (en) | 2014-07-31 |
KR20140095824A (ko) | 2014-08-04 |
JP6385677B2 (ja) | 2018-09-05 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6385677B2 (ja) | 基板加工方法 | |
US9412636B2 (en) | Methods for processing substrates | |
JP7129427B2 (ja) | 処理された積層ダイ | |
JP6197422B2 (ja) | 半導体装置の製造方法および支持基板付きウェハ | |
CN102163559B (zh) | 堆叠装置的制造方法及装置晶片处理方法 | |
TW202236439A (zh) | 直接接合方法及結構 | |
JP5756334B2 (ja) | 積層体、およびその積層体の分離方法 | |
JP5334411B2 (ja) | 貼り合わせ基板および貼り合せ基板を用いた半導体装置の製造方法 | |
KR20190092574A (ko) | 적층된 기판의 처리 | |
US9287222B1 (en) | Integrated semiconductor device and method for fabricating the same | |
JP5661928B2 (ja) | 積層体の製造方法、基板の処理方法および積層体 | |
JP2004282035A (ja) | 半導体装置の製造方法 | |
US20170025370A1 (en) | Chip scale sensing chip package and a manufacturing method thereof | |
TWI401752B (zh) | 晶片封裝結構之製造方法 | |
JP2021535608A (ja) | ウェハレベルパッケージ方法及びパッケージ構造 | |
TWI503933B (zh) | 半導體封裝件及其製法 | |
CN111370360A (zh) | 基底贴膜方法及封装方法 | |
CN111524849A (zh) | 半导体结构及其制作方法 | |
CN104934365B (zh) | 一种半导体器件的制作方法 | |
JP2008235723A (ja) | ウェハー構造体及びその製造方法 | |
US9997390B2 (en) | Semiconductor manufacturing method and laminated body | |
JP2008187203A (ja) | 半導体装置の製造方法 | |
US12080672B2 (en) | Direct gang bonding methods including directly bonding first element to second element to form bonded structure without adhesive | |
US20240170299A1 (en) | Method for manufacturing semiconductor device | |
JP2005268552A (ja) | 半導体装置およびその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20161222 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20161228 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170120 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170222 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20171124 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20171219 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20180316 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20180710 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20180808 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6385677 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |