CN104218022A - 晶片封装体及其制造方法 - Google Patents
晶片封装体及其制造方法 Download PDFInfo
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- CN104218022A CN104218022A CN201410440749.8A CN201410440749A CN104218022A CN 104218022 A CN104218022 A CN 104218022A CN 201410440749 A CN201410440749 A CN 201410440749A CN 104218022 A CN104218022 A CN 104218022A
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Abstract
本发明揭示一种晶片封装体及其制造方法。该晶片封装体包括:一半导体晶片,具有一第一表面及与该第一表面相对的一第二表面,并具有至少一导电垫邻近于第一表面,且具有一开口自第二表面朝第一表面延伸而露出导电垫;一绝缘层及一重布线层,依序设置于第二表面上,且延伸至开口的侧壁及底部,其中位于开口底部的绝缘层具有一底脚结构,且重布线层经由开口与导电垫电性连接;一保护层,覆盖重布线层且局部填入开口,以在开口内的保护层与导电垫之间形成一孔洞。本发明可防止重布线层与半导体晶片的导电垫发生剥离,进而增加晶片封装体的可靠度。
Description
(本申请是申请日为2012年02月10日、申请号为201210030867.2、发明名称为“晶片封装体及其制造方法”的申请的分案申请。)
技术领域
本发明有关于一种晶片封装体,特别是有关于一种基底通孔电极(through substrate via,TSV)结构中具有孔洞的晶片封装体及其制造方法。
背景技术
随着电子或光电产品诸如数字相机、具有影像拍摄功能的手机、条码扫瞄器(bar code reader)以及监视器需求的增加,半导体技术发展的相当快速,且半导体晶片的尺寸有微缩化(miniaturization)的趋势,而其功能也变得更为复杂。
大多数的半导体晶片通常为了效能上的需求而置放于一密封的封装体,其有助于操作上的稳定性。然而,晶片封装体中的保护层与金属重布线层之间热膨胀系数(coefficient of thermal expansion,CTE)的不匹配,容易造成金属重布线层与半导体晶片的导电垫剥离,因而降低晶片封装体的可靠度。
因此,有必要寻求一种新的封装体结构,其能够解决上述的问题。
发明内容
有鉴于此,本发明提供一种晶片封装体,包括:一半导体晶片,具有一第一表面及与该第一表面相对的一第二表面,具并有至少一导电垫邻近于第一表面,且具有一第一开口自第二表面朝第一表面延伸而露出导电垫;一绝缘层,设置于第二表面上,且延伸至第一开口的侧壁及底部,并露出导电垫,其中位于第一开口底部的绝缘层具有一底脚结构;一重布线层,设置于绝缘层上,并经由第一开口与露出的导电垫电性连接;以及一保护层,覆盖重布线层且局部填入第一开口,以在第一开口内的保护层与导电垫之间形成一孔洞,其中保护层具有至少一第二开口以露出第二表面上方的重布线层。
本发明还提供一种晶片封装体的制造方法,包括:提供一半导体晶圆,该半导体晶圆具有一第一表面及与该第一表面相对的一第二表面,且具有至少一导电垫邻近于第一表面且对应于每一晶片区;蚀刻半导体晶圆,以在每一晶片区形成自第二表面朝第一表面延伸的一第一开口而露出导电垫;于第二表面上形成一绝缘层,且该绝缘层延伸至每一第一开口的侧壁及底部并露出导电垫,其中位于第一开口底部的绝缘层具有一底脚结构;于绝缘层上形成一重布线层,其中重布线层经由每一第一开口与露出的导电垫电性连接;于重布线层上覆盖一保护层,且该保护层局部填入每一第一开口,以在每一第一开口内的保护层与导电垫之间形成一孔洞,其中保护层具有至少一第二开口以露出该第二表面上方的重布线层;以及切割半导体晶圆,以形成对应每一晶片区的一半导体晶片。
本发明可防止重布线层与半导体晶片的导电垫发生剥离,进而增加晶片封装体的可靠度。
附图说明
图1A至图1I绘示出根据本发明实施例的晶片封装体的制造方法剖面示意图。
附图中符号的简单说明如下:
10:切割道;100:基底;100a:第一表面;100b:第二表面;101:半导体晶圆;102:导电垫;104:微阵列结构;106、112a:开口;108:绝缘层;109:自对准蚀刻制程;110:重布线层;112:保护层;114:孔洞;114a:孔洞的顶部;116:遮光层;118:导电凸块;120:半导体晶片;200:玻璃基底;202:围堰结构;204:空腔;300:晶片封装体;d1:第一口径;d2:第二口径。
具体实施方式
为让本发明的上述和其他目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并配合所附图式,作详细说明如下。
以下说明本发明实施例的制作与使用。然而,可轻易了解本发明所提供的实施例仅用于说明以特定方法制作及使用本发明,并非用以局限本发明的范围。在图式或描述中,相似或相同部份的元件使用相同或相似的符号表示。再者,图式中元件的形状或厚度可扩大,以简化或方便标示。此外,未绘示或描述的元件,可以是具有各种本领域普通技术人员所知的形式。
请参照图1I,其绘示出根据本发明实施例300的晶片封装体剖面示意图。在本发明的晶片封装体实施例中,其可应用于各种包含有源元件或无源元件(active or passive elements)、数字电路或模拟电路等集成电路的电子元件(electronic components),例如是有关于光电元件(opto electronic devices)、微机电系统(Micro Electro Mechanical Systems,MEMS)、微流体系统(microfluidic systems)、或利用热、光线及压力等物理量变化来测量的物理感测器(physical sensor)。特别是可选择使用晶圆级封装制程对影像感测器、发光二极管、太阳能电池、射频元件(RF circuits)、加速计(accelerators)、陀螺仪(gyroscopes)、微制动器(micro actuators)、表面声波元件、压力感测器(pressure sensors)、或喷墨头(ink printer heads)等半导体晶片进行封装。
上述晶圆级封装制程主要是指在晶圆阶段完成封装步骤后,再予以切割成独立的封装体,然而,在一特定实施例中,例如将已分离的半导体晶片重新分布在一承载晶圆上,再进行封装制程,亦可称之为晶圆级封装制程。上述晶圆级封装制程亦适用于通过堆叠(stack)方式安排具有集成电路的多片晶圆,以形成多层集成电路(multi-layer integrated circuit devices)的封装体。
晶片封装体300包括:一半导体晶片120、一绝缘层108、一重布线层110、一保护层112、至少一导电凸块118、一微阵列结构(microlens array)104及一玻璃基底200。半导体晶片120具有一第一表面100a以及与第一表面100a相对的一第二表面100b。在本实施例中,半导体晶片120包括一基底100及位于上方的介电层。基底100,例如一硅基底或其他半导体基底,可包括导电层、介电层及其他半导体元件(例如,有源元件、无源元件、数字电路或模拟电路等集成电路的电子元件)。为了简化图式,此处仅一平整基底表示。每一半导体晶片120具有至少一导电垫102邻近于第一表面100a且位于基底100上方的介电层内。导电垫102电性连接至基底100内的电路(未绘示),以提供半导体晶片120与外部电路的电性连接。
再者,半导体晶片120具有一开口106(如图1C所示)自第二表面100b朝第一表面100a延伸而露出对应的导电垫102。在本实施例中,开口106具有一第一口径d1邻近第一表面100a以及一第二口径d2邻近第二表面100b,且第一口径d1大于第二口径d2,如图1C所示。
绝缘层108设置于半导体晶片120的第二表面100b上,且延伸至开口106的侧壁及底部并露出开口106底部的导电垫102。在一实施例中,位于开口106底部的绝缘层108具有一底脚(underfoot)结构108a(如图1E所示)。
重布线层110设置于绝缘层108上,并延伸至开口106内,使重布线层110经由开口106而与露出的导电垫102电性连接。
保护层112覆盖重布线层110且局部填入开口106,以在开口106内的保护层112与导电垫102之间形成一孔洞114,使开口106内的保护层112不与导电垫102接触。保护层具有至少一开口112a,以露出位于半导体晶片120的第二表面100b上方的重布线层110。再者,保护层112的材质可包括但不限于防焊(solder mask)材料,且粘滞系数在7000cp至11000cp的范围。在本实施例中,孔洞114作为保护层112与重布线层110之间的缓冲,以降低保护层112与重布线层110之间因热膨胀系数不匹配所引发不必要的应力。因此,可避免重布线层110与导电垫102发生剥离。在一实施例中,孔洞114的高度与该开口106的深度比在1/2至3/4的范围。再者,孔洞114的顶部114a具有中心轴旋转对称轮廓,例如,孔洞的顶部114a可具有一拱形轮廓。
导电凸块118设置于对应的开口112a内,并经由开口112a而电性连接至露出的重布线层110。
玻璃基底200的一表面上具有一围堰结构202。玻璃基底200经由围堰结构202而贴合至半导体晶片120的第一表面100a,以在玻璃基底200与半导体晶片120之间形成一空腔204。
微阵列结构设置于半导体晶片120的第一表面100a上且位于空腔204内。
以下配合图1A至1I说明根据本发明实施例的晶片封装体300的制造方法。请参照图1A,提供一玻璃基底200,其上具有一围堰结构202。请参照图1B,提供一半导体晶圆101,其具有一第一表面100a以及与第一表面100a相对的一第二表面100b。于半导体晶圆101的切割道10所定义出的每一晶片区的第一表面100a上形成一微阵列结构104。接着,将围堰结构202贴合至半导体晶圆101的第一表面100a,以在玻璃基底200与半导体晶圆101之间形成多个空腔204。每一空腔204对应每一晶片区,使每一微阵列结构104位于对应的空腔204内。
在本实施例中,半导体晶圆101包括一基底100(例如,硅基底或其他半导体基底)及位于上方的介电层。基底100可包括导电层、介电层及其他半导体元件(例如,有源元件、无源元件、数字电路或模拟电路等集成电路的电子元件)。为了简化图式,此处仅一平整基底表示。半导体晶圆101具有多个导电垫102邻近于第一表面100a且位于基底100上方的介电层内,用以电性连接至基底100内的电路(未绘示)。导电垫102可由铝、铜、金及其组合或其他已知接垫材料所构成。再者,至少一导电垫102对应于每一晶片区。此处,为简化图式及说明,每一晶片区仅以对应一导电垫102表示。
接下来,请参照图1C,对半导体晶圆101的第二表面(即,基底100的底表面)进行一薄化制程,使基底100达到所需的厚度。薄化制程一般可包括蚀刻、铣削(milling)、磨削(grinding)、或研磨(polishing)。接着,蚀刻半导体晶圆101的第二表面100b,以在每一晶片区形成自第二表面100b朝第一表面100a延伸的一开口106而露出对应的导电垫102。在本实施例中,开口106具有一第一口径d1邻近第一表面100a以及一第二口径d2邻近第二表面100b,且第一口径d1大于第二口径d2。因此,开口106的侧壁倾斜于基底100的表面。开口106可具有各种形状,例如是圆形、椭圆性、正方形或长方形等。当开口为圆形时,口径d1及d2即为圆形开口的直径。
在一实施例中,开口106的形成方式包括以干蚀刻移除基底100。举例来说,可先进行一主要蚀刻(main etching)。接着,改变蚀刻制程条件(例如,功率、压力、及/或蚀刻反应气体的浓度等)以进行过蚀刻(over etching),以获得具有第一口径d1大于第二口径d2的开口106。
接下来,请参照图1D至1E,于半导体晶圆101的第二表面100b上形成一绝缘层108,且延伸至每一开口106的侧壁及底部并露出导电垫102。绝缘层108与后续形成的导线层(conductive trace layer)隔离,其材料可为环氧树脂、防焊层或其他适合的绝缘材料,例如氧化硅层、氮化硅层、氮氧化硅层、金属氧化物或其组合。绝缘层108的形成方式可包含涂布方式(例如,旋转涂布(spin coating)、喷涂(spray coating)或淋幕涂布(curtain coating))或其他适合的沉积方式,例如,液相沉积、物理气相沉积、化学气相沉积、低压化学气相沉积、等离子增强式化学气相沉积、快速热化学气相沉积或常压化学气相沉积等制程。由于开口106的侧壁倾斜于基底100的表面且第一口径d1大于第二口径d2,因此基底100的下表面(即,第二表面100b)上的绝缘层108厚度通常大于开口106的侧壁及底部的绝缘层108厚度。接下来,请参照图1E,对绝缘层108进行一自对准蚀刻制程(self-aligned etching)109,使位于开口106底部的绝缘层108形成一底脚结构108a而露出开口106内的导电垫102。在一实施例中,自对准蚀刻制程109可包括一非等向性蚀刻,例如反应离子蚀刻(reactive ion etching,RIE)。
接下来,请参照图1F,于该绝缘层108上形成一重布线层110。重布线层110延伸至每一开口106内,使重布线层110经由开口106与露出的导电垫102电性连接,而形成基底通孔电极(TSV)结构。
接下来,请参照图1G,于重布线层110上覆盖一保护层112,其中保护层112具有多个开口112a以露出半导体晶圆101的第二表面100b上方的重布线层110。每一晶片区对应至少一开口112a。在本实施例中,保护层112的材质可包括但不限于防焊材料,且粘滞系数在7000cp至11000cp的范围。再者,由于开口106的侧壁倾斜于基底100的表面且第一口径d1大于第二口径d2,因此开口106内会残留空气,使重布线层110上的保护层112局部填入每一开口106,而在每一开口106内的保护层112与导电垫102之间而形成一孔洞114,且开口106内的保护层112未与导电垫102接触。
接着,对保护层112进行一烘烤制程,使其固化。由于烘烤期间,孔洞114内空气温度及压力上升,因此保护层112会收缩而增加孔洞114的高度。在图1G中,开口106内的虚线表示烘烤前孔洞114的顶部。孔洞114的高度必须适当,当孔洞114的高度过高,容易使保护层112发生龟裂,而当孔洞114的高度过低,孔洞无法有效地作为保护层112与重布线层110之间的缓冲。在一实施例中,孔洞114的高度与开口106的深度比在1/2至3/4的范围。再者,孔洞114的顶部114a具有中心轴旋转对称轮廓。例如,孔洞的顶部114a可具有一拱形轮廓。
接下来,请参照图1H,于每一开口112a内形成一导电凸块118,使每一导电凸块118经由对应的开口112a而电性连接至重布线层110。此外,在一实施例中,当晶片封装体应用于光电元件时,可在形成导电凸块118之前,在保护层112上形成遮光层116,例如黑色光阻,以防止漏光。
接下来,请参照图1I,沿着切割道10(如图1H所示)切割半导体晶圆101形成对应每一晶片区的一半导体晶片120。接着,沿着切割道10切割围堰结构202及玻璃基底200,而形成多个独立的晶片封装体300。
根据上述实施例,由于基底通孔电极结构中的孔洞可作为保护层与重布线层之间的缓冲,因此可防止重布线层与半导体晶片的导电垫发生剥离,进而增加晶片封装体的可靠度。
以上所述仅为本发明较佳实施例,然其并非用以限定本发明的范围,任何熟悉本项技术的人员,在不脱离本发明的精神和范围内,可在此基础上做进一步的改进和变化,因此本发明的保护范围当以本申请的权利要求书所界定的范围为准。
Claims (26)
1.一种晶片封装体,其特征在于,包括:
一半导体晶片,具有一第一表面及与该第一表面相对的一第二表面,并具有至少一导电垫邻近于该第一表面,且具有一第一开口自该第二表面朝该第一表面延伸而露出该导电垫;
一绝缘层,设置于该第二表面上,且延伸至该第一开口的侧壁及底部,并露出该导电垫,其中位于该第一开口底部的该绝缘层具有一底脚结构;
一重布线层,设置于该绝缘层上,并经由该第一开口与该露出的导电垫电性连接;以及
一保护层,覆盖该重布线层且局部填入该第一开口,以在该第一开口内的该保护层与该导电垫之间形成一孔洞,其中该保护层具有至少一第二开口以露出该第二表面上方的该重布线层。
2.根据权利要求1所述的晶片封装体,其特征在于,该孔洞的高度与该第一开口的深度比在1/2至3/4的范围。
3.根据权利要求1所述的晶片封装体,其特征在于,该第一开口内的该保护层不与该导电垫接触。
4.根据权利要求1所述的晶片封装体,其特征在于,该孔洞的顶部具有一拱形轮廓。
5.根据权利要求1所述的晶片封装体,其特征在于,该孔洞的顶部具有中心轴旋转对称轮廓。
6.根据权利要求1所述的晶片封装体,其特征在于,该保护层的粘滞系数在7000cp至11000cp的范围。
7.根据权利要求1所述的晶片封装体,其特征在于,该保护层包括阻焊材料。
8.根据权利要求1所述的晶片封装体,其特征在于,还包括:
一玻璃基底,该玻璃基底上具有一围堰结构,且该围堰结构贴合至该半导体晶片的该第一表面,以在该玻璃基底与该半导体晶片之间形成一空腔;以及
一微阵列结构,设置于该半导体晶片的该第一表面上且位于该空腔内。
9.根据权利要求1所述的晶片封装体,其特征在于,该底脚结构具有一倾斜面。
10.根据权利要求9所述的晶片封装体,其特征在于,该第一开口的侧壁与该倾斜面形成一转折角。
11.根据权利要求10所述的晶片封装体,其特征在于,该倾斜面距离该第一表面的厚度自该转折角渐减。
12.根据权利要求1所述的晶片封装体,其特征在于,该第一开口具有邻近该第一表面的一第一口径以及邻近该第二表面的一第二口径,且该第一口径大于该第二口径。
13.一种晶片封装体的制造方法,其特征在于,包括:
提供一半导体晶圆,该半导体晶圆具有一第一表面及与该第一表面相对的一第二表面,且具有至少一导电垫邻近于该第一表面且对应于每一晶片区;
蚀刻该半导体晶圆,以在每一晶片区形成自该第二表面朝该第一表面延伸的一第一开口而露出该导电垫;
于该第二表面上形成一绝缘层,且该绝缘层延伸至每一第一开口的侧壁及底部并露出该导电垫,其中位于该第一开口底部的该绝缘层具有一底脚结构;
于该绝缘层上形成一重布线层,其中该重布线层经由每一第一开口与该露出的导电垫电性连接;
于该重布线层上覆盖一保护层,且该保护层局部填入每一第一开口,以在每一第一开口内的该保护层与该导电垫之间形成一孔洞,其中该保护层具有至少一第二开口以露出该第二表面上方的该重布线层;以及
切割该半导体晶圆,以形成对应每一晶片区的一半导体晶片。
14.根据权利要求13所述的晶片封装体的制造方法,其特征在于,形成该绝缘层的步骤还包括进行一自对准蚀刻制程,以露出该导电垫。
15.根据权利要求14所述的晶片封装体的制造方法,其特征在于,蚀刻该半导体晶圆的步骤还包括对该半导体晶圆的该第二表面进行一薄化制程。
16.根据权利要求15所述的晶片封装体的制造方法,其特征在于,该孔洞的高度与该第一开口的深度比在1/2至3/4的范围。
17.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该第一开口内的该保护层不与该导电垫接触。
18.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该孔洞的顶部具有一拱形轮廓。
19.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该孔洞的顶部具有中心轴旋转对称轮廓。
20.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该保护层的粘滞系数在7000cp至11000cp的范围。
21.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该保护层包括阻焊材料。
22.根据权利要求13所述的晶片封装体的制造方法,其特征在于,还包括:
于每一晶片区的该第一表面上形成一微阵列结构;
提供一玻璃基底,该玻璃基底上具有一围堰结构;
将该围堰结构贴合至该半导体晶圆的该第一表面,以在该玻璃基底与该半导体晶圆之间形成对应每一晶片区的一空腔,使每一微阵列结构位于该对应的空腔内;以及
切割该围堰结构及该玻璃基底。
23.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该底脚结构具有一倾斜面。
24.根据权利要求23所述的晶片封装体的制造方法,其特征在于,该第一开口的侧壁与该倾斜面形成一转折角。
25.根据权利要求24所述的晶片封装体的制造方法,其特征在于,该倾斜面距离该第一表面的厚度自该转折角渐减。
26.根据权利要求13所述的晶片封装体的制造方法,其特征在于,该第一开口具有邻近该第一表面的一第一口径以及邻近该第二表面的一第二口径,且该第一口径大于该第二口径。
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