JP6369366B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP6369366B2 JP6369366B2 JP2015064093A JP2015064093A JP6369366B2 JP 6369366 B2 JP6369366 B2 JP 6369366B2 JP 2015064093 A JP2015064093 A JP 2015064093A JP 2015064093 A JP2015064093 A JP 2015064093A JP 6369366 B2 JP6369366 B2 JP 6369366B2
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- electrode
- molybdenum
- dry etching
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
- H01L29/475—Schottky barrier electrodes on AIII-BV compounds
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- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66212—Schottky diodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Description
本発明の一形態は、半導体装置の製造方法であって、
前記半導体装置における半導体層、絶縁膜および電極のうち、少なくとも前記電極の上に、モリブデン(Mo)から主になるモリブデン層を形成する成膜工程と、
200℃以上の温度で前記モリブデン層を加熱する熱処理工程と、
前記熱処理工程を行った後、前記モリブデン層が形成された前記半導体装置に対してドライエッチングを施すドライエッチング工程と、を備え、
前記ドライエッチング工程は、
前記熱処理工程を行った後、前記半導体層および前記絶縁膜の少なくとも一方と、前記モリブデン層と、が露出した前記半導体装置に対して、前記モリブデン層を前記電極のマスクとして、前記半導体層と前記絶縁膜の少なくとも一方にドライエッチングを施す工程であり、
前記ドライエッチング後には、前記モリブデン層の一部が露出して残り、前記モリブデン層の一部が前記電極の一部として形成され、前記モリブデン層に覆われていない、前記半導体層および前記絶縁膜の少なくとも一方が除去される工程である、半導体装置の製造方法である。
また、本発明は以下の形態として実現することも可能である。
A−1.半導体装置の構成
図1は、第1実施形態における半導体装置100の構成を模式的に示す断面図である。図1には、相互に直交するXYZ軸が図示されている。図1のXYZ軸のうち、X軸は、図1の紙面左から紙面右に向かう軸である。+X軸方向は、紙面右に向かう方向であり、−X軸方向は、紙面左に向かう方向である。図1のXYZ軸のうち、Y軸は、図1の紙面手前から紙面奥に向かう軸である。+Y軸方向は、紙面奥に向かう方向であり、−Y軸方向は、紙面手前に向かう方向である。図1のXYZ軸のうち、Z軸は、図1の紙面下から紙面上に向かう軸である。+Z軸方向は、紙面上に向かう方向であり、−Z軸方向は、紙面下に向かう方向である。図1のXYZ軸は、他の図のXYZ軸に対応する。
図2は、第1実施形態における半導体装置100の製造方法を示す工程図である。図3から図6は、半導体装置100を製造する様子を示す説明図である。
図7は、モリブデン層の熱処理温度とエッチングレートの関係を評価した結果を示すグラフである。図7の評価試験では、試験者は、ケイ素(Si)から主に成る基板の上に、約500nmのモリブデン(Mo)から主になるモリブデン層を形成することによって、複数の試料を作製した。その後、試験者は、複数の試料の中から、複数の熱処理温度で熱処理を加えた試料をそれぞれ作製した。試料に熱処理を加えた熱処理温度は、50℃、100℃、200℃、300℃、400℃、500℃、600℃、700℃、800℃である。試験者は、窒素から主に成る雰囲気の中に置かれた試料を、5分間、各熱処理温度で加熱した。
以上説明した第1実施形態によれば、200℃以上の温度でモリブデン層160を加熱することによって、ドライエッチングに対する耐性を十分に有する金属層を、モリブデン層160によって容易に形成できる。その結果、半導体装置100の製造コストを低減できる。
B−1.半導体装置の構成
図9は、第2実施形態における半導体装置200の構成を模式的に示す断面図である。図9には、図1と同様に、相互に直交するXYZ軸が図示されている。
図10は、第2実施形態における半導体装置200の製造方法を示す工程図である。図11から図14は、半導体装置200を製造する様子を示す説明図である。
図15は、モリブデン層が積層された電極の接触抵抗を評価した結果を示すグラフである。図15の評価試験では、試験者は、サファイアから主に成る基板の上に、バッファ層およびGaN系真性半導体層を介して、半導体層216と同様にn型半導体層を形成した。その後、試験者は、n型半導体層の上に、半導体装置200のソース電極240と同様に、電極を形成した。この電極は、厚さ約30nmのチタン(Ti)から主に成る層の上に、厚さ約200nmのアルミニウム(Al)から主に成る層を積層した後に、アニール処理(熱処理)を加えた電極である。
以上説明した第2実施形態によれば、200℃以上の温度でモリブデン層245,255を加熱することによって、ドライエッチングに対する耐性を十分に有する金属層を、モリブデン層245,255によって容易に形成できる。その結果、半導体装置200の製造コストを低減できる。
図17は、第3実施形態における半導体装置300の構成を模式的に示す断面図である。半導体装置300は、ソース電極240に代えてソース電極240Cを備える点、並びに、モリブデン層245,255に代えてモリブデン層245Cを備える点を除き、第2実施形態の半導体装置200と同様である。
図18は、第4実施形態における半導体装置400の構成を模式的に示す断面図である。半導体装置400は、モリブデン層245,255を備えていない点、絶縁膜230に代えて絶縁膜230Dを備える点、並びに、ゲート電極280に代えてゲート電極280Dを備える点を除き、第2実施形態の半導体装置200と同様である。
図22は、第5実施形態における半導体装置500の構成を模式的に示す断面図である。半導体装置500は、ソース電極240の上にモリブデン層245Eを備える点、ボディ電極250の上にモリブデン層255Eを備える点、絶縁膜230に代えて絶縁膜230Eを備える点、並びに、ゲート電極280に代えてゲート電極280Eを備える点を除き、第2実施形態の半導体装置200と同様である。
図23は、第6実施形態における半導体装置600の構成を模式的に示す断面図である。半導体装置600は、ソース電極240の上にモリブデン層245Fを備える点、ボディ電極250の上にモリブデン層255Fを備える点、ゲート電極280に代えてゲート電極280Fを備える点を除き、並びに、配線電極274F,275F,278Fを備える点を除き、第2実施形態の半導体装置200と同様である。
本発明は、上述の実施形態や実施例、変形例に限られるものではなく、その趣旨を逸脱しない範囲において種々の構成で実現することができる。例えば、発明の概要の欄に記載した各形態中の技術的特徴に対応する実施形態、実施例、変形例中の技術的特徴は、上述の課題の一部または全部を解決するために、あるいは、上述の効果の一部または全部を達成するために、適宜、差し替えや、組み合わせを行うことが可能である。また、その技術的特徴が本明細書中に必須なものとして説明されていなければ、適宜、削除することが可能である。
100a,100b,100c,100d…半導体装置
110…基板
112…半導体層
112m…メサ構造
112p…周囲面
112s…側面
112u…上面
116…半導体層
128…トレンチ
130…絶縁膜
150…ショットキー電極
160…モリブデン層
170…絶縁膜
178…コンタクトホール
180…配線電極
190…裏面電極
200…半導体装置
200a,200b,200c,200d…半導体装置
210…基板
212…半導体層
214…半導体層
216…半導体層
222…トレンチ
224…リセス
228…トレンチ
230,230D,230E…絶縁膜
230p…絶縁膜
236,238…コンタクトホール
240,240C…ソース電極
245,245C,245E,245F…モリブデン層
250…ボディ電極
255,255E,255F…モリブデン層
270F…電極層
274F,275F,278F…配線電極
280,280D,280E,280F…ゲート電極
280p…電極層
290…ドレイン電極
300…半導体装置
400…半導体装置
400a…半導体装置
500…半導体装置
600…半導体装置
600a,600b…半導体装置
Claims (7)
- 半導体装置の製造方法であって、
前記半導体装置における半導体層、絶縁膜および電極のうち、少なくとも前記電極の上に、モリブデン(Mo)から主になるモリブデン層を形成する成膜工程と、
200℃以上の温度で前記モリブデン層を加熱する熱処理工程と、
前記熱処理工程を行った後、前記モリブデン層が形成された前記半導体装置に対してドライエッチングを施すドライエッチング工程と、を備え、
前記ドライエッチング工程は、
前記熱処理工程を行った後、前記半導体層および前記絶縁膜の少なくとも一方と、前記モリブデン層と、が露出した前記半導体装置に対して、前記モリブデン層を前記電極のマスクとして、前記半導体層と前記絶縁膜の少なくとも一方にドライエッチングを施す工程であり、
前記ドライエッチング後には、前記モリブデン層の一部が露出して残り、前記モリブデン層の一部が前記電極の一部として形成され、前記モリブデン層に覆われていない、前記半導体層および前記絶縁膜の少なくとも一方が除去される工程である、半導体装置の製造方法。 - 前記熱処理工程は、窒素、アルゴンおよび酸素の少なくとも1つから主に成る雰囲気中、または真空中に置かれた前記モリブデン層を、200℃以上の温度で加熱する工程である、請求項1に記載の半導体装置の製造方法。
- 前記熱処理工程は、1分以上10分以下の間、200℃以上の温度で前記モリブデン層を加熱する工程である、請求項1または請求項2に記載の半導体装置の製造方法。
- 前記ドライエッチング工程は、前記熱処理工程を行った後、前記モリブデン層が露出した前記半導体装置に対して、塩素を含有するガスを用いたドライエッチングを施す工程である、請求項1から請求項3までのいずれか一項に記載の半導体装置の製造方法。
- 前記成膜工程に先立って前記電極を加熱する、請求項1から請求項4までのいずれか一項に記載の半導体装置の製造方法。
- 前記熱処理工程は、700℃以上の温度で前記モリブデン層を加熱する工程である、請求項1から請求項5までのいずれか一項に記載の半導体装置の製造方法。
- 窒化ガリウム(GaN)から主に成る前記半導体層を形成する、請求項1から請求項6までのいずれか一項に記載の半導体装置の製造方法。
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