JP6367575B2 - 二次電池搭載回路チップ及びその製造方法 - Google Patents
二次電池搭載回路チップ及びその製造方法 Download PDFInfo
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- H01M50/00—Constructional details or processes of manufacture of the non-active parts of electrochemical cells other than fuel cells, e.g. hybrid cells
- H01M50/50—Current conducting connections for cells or batteries
- H01M50/572—Means for preventing undesired use or discharge
- H01M50/574—Devices or arrangements for the interruption of current
- H01M50/578—Devices or arrangements for the interruption of current in response to pressure
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02S—GENERATION OF ELECTRIC POWER BY CONVERSION OF INFRARED RADIATION, VISIBLE LIGHT OR ULTRAVIOLET LIGHT, e.g. USING PHOTOVOLTAIC [PV] MODULES
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- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
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- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Description
(実施例)
12 負電極
14 n型金属酸化物半導体層
16 充電層
18 p型金属酸化物半導体層
20 正電極
40 ウェハ
42 集積回路チップ
44 チップ基板
46 電極パッド
48 集積回路
52 ゲート電極
54 第1配線層
56 第2配線層
58 第3配線層
59 面電極層
60,60−1,60−2,60−3,60−4 ビアホール
61−1,61−2 正電極用ビアホール
62 電極パッド
63 面電極
64 スクライブ領域
66 二次電池搭載領域
68 搭載された二次電池
70 二次電池搭載回路チップの製造方法を示すフローチャート
72 フォトレジスト
73 負電極
74 負電極層
75 正電極
76,76−1,76−2 負電極用電極パッド
78 充電層
80,80−1,80−2 正電極用電極パッド
82 正電極層
81 負電極接続パッド
83,83−1,83−2 絶縁層
84 ダイシング部
85 導電性ペースト
86 バックグラインド部
87 正電極接続パッド
88 二次電池搭載集積回路チップ
89 パッケージ基板
90−1,90−2,90−3,90−4 内部負電極配線
91 導電性ペースト
Claims (16)
- 回路と一体的に形成される二次電池搭載回路チップであって、
多層配線された前記回路の最上部配線層の少なくとも一部の領域、又は、全面を、面構造の負電極又は正電極とし、前記二次電池の負電極又は正電極と共通に使用して、回路に面した領域に前記二次電池を形成したことを特徴とする二次電池搭載回路チップ。 - 前記二次電池を多層配線された回路の最上部に形成し、さらに多層配線された回路の裏面にも形成したことを特徴とする請求項1に記載の二次電池搭載回路チップ。
- 前記二次電池の下部電極及び/又は上部電極は回路の配線層及びビアホールにより回路内部の電源層配線と接続されることを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池は実装時に他の電気部品に電力を供給できるように配置されたパッドに接続することを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池の制御を行う回路が設けられており、二次電池の電極が配線及びビアホールを通して接続していること、
を特徴とする請求項1又は2に記載の二次電池搭載回路チップ。 - 前記回路チップには電子回路、論理回路、センサーまたはMEMSにより形成された要素部品を有していることを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池は、電極で分割された複数個の二次電池であること、
を特徴とする請求項1又は2に記載の二次電池搭載回路チップ。 - 複数の前記二次電池が積層されていること、
を特徴とする請求項1又は2に記載の二次電池搭載回路チップ。 - パッシベーションされた回路面に前記二次電池を直接作製したことを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池の下部電極及び上部電極が回路チップの外部を通して、回路チップ内の電源配線あるいは二次電池制御回路に接続することを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池の下部電極及び上部電極を回路チップの基板を貫通するビアホールを通して回路内の電源配線あるいは二次電池制御回路に接続することを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 前記二次電池は量子電池であることを特徴とする請求項1又は2に記載の二次電池搭載回路チップ。
- 回路上に二次電池を搭載した二次電池搭載回路チップの製造方法であって、
ウェハに形成された複数個の回路に対してパッシベーションされた上面は、多層配線された前記回路の最上部配線層の少なくとも一部の領域、又は、全面を、面構造の負電極又は正電極であり、前記二次電池の負電極又は正電極と共通に使用して、回路チップ毎に分割され、かつ回路チップが電気的に接続する領域を除いた領域、かつパッシベーション下層の配線と接続部分を含む領域にパターニングされた下部電極層を形成する下部電極層形成工程と、
前記ウェハの下部電極上に電気を蓄える充電層を、充電層用材料の塗布・焼成により形成する充電層形成工程と、
少なくとも、前記充電層上およびパッシベーション層の下層配線と接続する領域に、パターニングされた上部電極層を形成する上部電極層形成工程と、
からなることを特徴とする二次電池搭載回路チップの製造方法。 - 前記上部電極層形成工程において、
複数の二次電池を形成するように、前記上部電極を分割してパターニングすること、
を特徴とする請求項13に記載の二次電池搭載回路チップの製造方法。 - 前記充電層形成工程は、
前記下部電極層が形成されたウェハの表面又は裏面の、少なくとも全ての下部電極層を含む領域に、充電層用材料の塗布・焼成により、電気を蓄える充電層を形成する充電層形成工程と、
前記下部電極層に対応して充電層用フォトレジストパターンを形成する充電層用フォトレジストパターン形成工程と、
前記充電層用フォトレジストパターンのない充電層領域を除去する充電層除去工程と、 前記充電層用フォトレジストパターンを除去する充電層用フォトレジストパターン除去工程と、
からなることを特徴とする請求項13に記載の二次電池搭載回路チップの製造方法。 - 前記製造方法において、二次電池形成後に電池を試験する工程と二次電池に電圧を印加することにより、コンディショニングを行なうコンディショニング工程と有する請求項13又は14に記載の二次電池搭載回路チップの製造方法。
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